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14#include <common.h>
15#include <command.h>
16#include <init.h>
17#include <log.h>
18#include <pci.h>
19#include <asm/processor.h>
20#include <asm/immap_86xx.h>
21#include <asm/fsl_pci.h>
22#include <fsl_ddr_sdram.h>
23#include <asm/fsl_serdes.h>
24#include <linux/delay.h>
25#include <linux/libfdt.h>
26#include <fdt_support.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30long int fixed_sdram (void);
31
32int board_early_init_f (void)
33{
34 return 0;
35}
36
37int checkboard (void)
38{
39 puts ("Board: Wind River SBC8641D\n");
40
41 return 0;
42}
43
44int dram_init(void)
45{
46 long dram_size = 0;
47
48#if defined(CONFIG_SPD_EEPROM)
49 dram_size = fsl_ddr_sdram();
50#else
51 dram_size = fixed_sdram ();
52#endif
53
54 debug(" DDR: ");
55 gd->ram_size = dram_size;
56
57 return 0;
58}
59
60#if defined(CONFIG_SYS_DRAM_TEST)
61int testdram(void)
62{
63 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
64 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
65 uint *p;
66
67 puts ("SDRAM test phase 1:\n");
68 for (p = pstart; p < pend; p++)
69 *p = 0xaaaaaaaa;
70
71 for (p = pstart; p < pend; p++) {
72 if (*p != 0xaaaaaaaa) {
73 printf ("SDRAM test fails at: %08x\n", (uint) p);
74 return 1;
75 }
76 }
77
78 puts ("SDRAM test phase 2:\n");
79 for (p = pstart; p < pend; p++)
80 *p = 0x55555555;
81
82 for (p = pstart; p < pend; p++) {
83 if (*p != 0x55555555) {
84 printf ("SDRAM test fails at: %08x\n", (uint) p);
85 return 1;
86 }
87 }
88
89 puts ("SDRAM test passed.\n");
90 return 0;
91}
92#endif
93
94#if !defined(CONFIG_SPD_EEPROM)
95
96
97
98long int fixed_sdram (void)
99{
100#if !defined(CONFIG_SYS_RAMBOOT)
101 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
102 volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
103
104 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
105 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
106 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
107 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
108 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
109 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
110 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
111 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
112 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
113 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
114 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
115 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
116 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
117 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
118 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
119 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
120 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
121 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
122 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
123 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
124
125 asm ("sync;isync");
126
127 udelay(500);
128
129 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
130 asm ("sync; isync");
131
132 udelay(500);
133 ddr = &immap->im_ddr2;
134
135 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
136 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
137 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
138 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
139 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
140 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
141 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
142 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
143 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
144 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
145 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
146 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
147 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
148 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
149 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
150 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
151 ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
152 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
153 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
154 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
155
156 asm ("sync;isync");
157
158 udelay(500);
159
160 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
161 asm ("sync; isync");
162
163 udelay(500);
164#endif
165 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
166}
167#endif
168
169#if defined(CONFIG_PCI)
170
171
172
173
174void pci_init_board(void)
175{
176 fsl_pcie_init_board(0);
177}
178#endif
179
180
181#if defined(CONFIG_OF_BOARD_SETUP)
182int ft_board_setup(void *blob, bd_t *bd)
183{
184 ft_cpu_setup(blob, bd);
185
186 FT_FSL_PCI_SETUP;
187
188 return 0;
189}
190#endif
191
192void sbc8641d_reset_board (void)
193{
194 puts ("Resetting board....\n");
195}
196
197
198
199
200
201
202unsigned long get_board_sys_clk (ulong dummy)
203{
204 int i;
205 ulong val = 0;
206
207 i = 5;
208 i &= 0x07;
209
210 switch (i) {
211 case 0:
212 val = 33000000;
213 break;
214 case 1:
215 val = 40000000;
216 break;
217 case 2:
218 val = 50000000;
219 break;
220 case 3:
221 val = 66000000;
222 break;
223 case 4:
224 val = 83000000;
225 break;
226 case 5:
227 val = 100000000;
228 break;
229 case 6:
230 val = 134000000;
231 break;
232 case 7:
233 val = 166000000;
234 break;
235 }
236
237 return val;
238}
239
240void board_reset(void)
241{
242#ifdef CONFIG_SYS_RESET_ADDRESS
243 ulong addr = CONFIG_SYS_RESET_ADDRESS;
244
245
246 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
247 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
248 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
249 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
250 __asm__ __volatile__ ("sync");
251 __asm__ __volatile__ ("mtspr 1008, 4");
252 __asm__ __volatile__ ("isync");
253 __asm__ __volatile__ ("sync");
254 __asm__ __volatile__ ("mtspr 1008, 5");
255 __asm__ __volatile__ ("isync");
256 __asm__ __volatile__ ("sync");
257
258
259
260
261
262 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
263 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
264 __asm__ __volatile__ ("mtspr 27, 4");
265 __asm__ __volatile__ ("rfi");
266#endif
267}
268
