LXR uboot/drivers/ddr/fsl/ddr4_dimm

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2014-2016 Freescale Semiconductor, Inc.
   4 * Copyright 2017-2018 NXP Semiconductor
   5 *
   6 * calculate the organization and timing parameter
   7 * from ddr3 spd, please refer to the spec
   8 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
   9 *
  10 *
  11 */
  12
  13#include <common.h>
  14#include <fsl_ddr_sdram.h>
  15#include <log.h>
  16#include <linux/bug.h>
  17
  18#include <fsl_ddr.h>
  19
  20/*
  21 * Calculate the Density of each Physical Rank.
  22 * Returned size is in bytes.
  23 *
  24 * Total DIMM size =
  25 * sdram capacity(bit) / 8 * primary bus width / sdram width
  26 *                     * Logical Ranks per DIMM
  27 *
  28 * where: sdram capacity  = spd byte4[3:0]
  29 *        primary bus width = spd byte13[2:0]
  30 *        sdram width = spd byte12[2:0]
  31 *        Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
  32 *                                 spd byte12{5:3] * spd byte6[6:4] for 3DS
  33 *
  34 * To simplify each rank size = total DIMM size / Number of Package Ranks
  35 * where Number of Package Ranks = spd byte12[5:3]
  36 *
  37 * SPD byte4 - sdram density and banks
  38 *      bit[3:0]        size(bit)       size(byte)
  39 *      0000            256Mb           32MB
  40 *      0001            512Mb           64MB
  41 *      0010            1Gb             128MB
  42 *      0011            2Gb             256MB
  43 *      0100            4Gb             512MB
  44 *      0101            8Gb             1GB
  45 *      0110            16Gb            2GB
  46 *      0111            32Gb            4GB
  47 *
  48 * SPD byte13 - module memory bus width
  49 *      bit[2:0]        primary bus width
  50 *      000             8bits
  51 *      001             16bits
  52 *      010             32bits
  53 *      011             64bits
  54 *
  55 * SPD byte12 - module organization
  56 *      bit[2:0]        sdram device width
  57 *      000             4bits
  58 *      001             8bits
  59 *      010             16bits
  60 *      011             32bits
  61 *
  62 * SPD byte12 - module organization
  63 *      bit[5:3]        number of package ranks per DIMM
  64 *      000             1
  65 *      001             2
  66 *      010             3
  67 *      011             4
  68 *
  69 * SPD byte6 - SDRAM package type
  70 *      bit[6:4]        Die count
  71 *      000             1
  72 *      001             2
  73 *      010             3
  74 *      011             4
  75 *      100             5
  76 *      101             6
  77 *      110             7
  78 *      111             8
  79 *
  80 * SPD byte6 - SRAM package type
  81 *      bit[1:0]        Signal loading
  82 *      00              Not specified
  83 *      01              Multi load stack
  84 *      10              Sigle load stack (3DS)
  85 *      11              Reserved
  86 */
  87static unsigned long long
  88compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
  89{
  90        unsigned long long bsize;
  91
  92        int nbit_sdram_cap_bsize = 0;
  93        int nbit_primary_bus_width = 0;
  94        int nbit_sdram_width = 0;
  95        int die_count = 0;
  96        bool package_3ds;
  97
  98        if ((spd->density_banks & 0xf) <= 7)
  99                nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
 100        if ((spd->bus_width & 0x7) < 4)
 101                nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
 102        if ((spd->organization & 0x7) < 4)
 103                nbit_sdram_width = (spd->organization & 0x7) + 2;
 104        package_3ds = (spd->package_type & 0x3) == 0x2;
 105        if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
 106                printf("Warning: not supported SDRAM package type\n");
 107                return 0;
 108        }
 109        if (package_3ds)
 110                die_count = (spd->package_type >> 4) & 0x7;
 111
 112        bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
 113                         nbit_primary_bus_width - nbit_sdram_width +
 114                         die_count);
 115
 116        debug("DDR: DDR rank density = 0x%16llx\n", bsize);
 117
 118        return bsize;
 119}
 120
 121#define spd_to_ps(mtb, ftb)     \
 122        (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
 123/*
 124 * ddr_compute_dimm_parameters for DDR4 SPD
 125 *
 126 * Compute DIMM parameters based upon the SPD information in spd.
 127 * Writes the results to the dimm_params_t structure pointed by pdimm.
 128 *
 129 */
 130unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 131                                         const generic_spd_eeprom_t *spd,
 132                                         dimm_params_t *pdimm,
 133                                         unsigned int dimm_number)
 134{
 135        unsigned int retval;
 136        int i;
 137        const u8 udimm_rc_e_dq[18] = {
 138                0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
 139                0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
 140        };
 141        int spd_error = 0;
 142        u8 *ptr;
 143        u8 val;
 144
 145        if (spd->mem_type) {
 146                if (spd->mem_type != SPD_MEMTYPE_DDR4) {
 147                        printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
 148                               ctrl_num, dimm_number);
 149                        return 1;
 150                }
 151        } else {
 152                memset(pdimm, 0, sizeof(dimm_params_t));
 153                return 1;
 154        }
 155
 156        retval = ddr4_spd_check(spd);
 157        if (retval) {
 158                printf("DIMM %u: failed checksum\n", dimm_number);
 159                return 2;
 160        }
 161
 162        /*
 163         * The part name in ASCII in the SPD EEPROM is not null terminated.
 164         * Guarantee null termination here by presetting all bytes to 0
 165         * and copying the part name in ASCII from the SPD onto it
 166         */
 167        memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 168        if ((spd->info_size_crc & 0xF) > 2)
 169                memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
 170
 171        /* DIMM organization parameters */
 172        pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
 173        pdimm->rank_density = compute_ranksize(spd);
 174        pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
 175        pdimm->die_density = spd->density_banks & 0xf;
 176        pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
 177        if ((spd->bus_width >> 3) & 0x3)
 178                pdimm->ec_sdram_width = 8;
 179        else
 180                pdimm->ec_sdram_width = 0;
 181        pdimm->data_width = pdimm->primary_sdram_width
 182                          + pdimm->ec_sdram_width;
 183        pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
 184        pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
 185                             (spd->package_type >> 4) & 0x7 : 0;
 186
 187        /* These are the types defined by the JEDEC SPD spec */
 188        pdimm->mirrored_dimm = 0;
 189        pdimm->registered_dimm = 0;
 190        switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
 191        case DDR4_SPD_MODULETYPE_RDIMM:
 192                /* Registered/buffered DIMMs */
 193                pdimm->registered_dimm = 1;
 194                if (spd->mod_section.registered.reg_map & 0x1)
 195                        pdimm->mirrored_dimm = 1;
 196                val = spd->mod_section.registered.ca_stren;
 197                pdimm->rcw[3] = val >> 4;
 198                pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
 199                val = spd->mod_section.registered.clk_stren;
 200                pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
 201                /* Not all in SPD. For convience only. Boards may overwrite. */
 202                pdimm->rcw[6] = 0xf;
 203                /*
 204                 * A17 only used for 16Gb and above devices.
 205                 * C[2:0] only used for 3DS.
 206                 */
 207                pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
 208                                (pdimm->package_3ds > 0x3 ? 0x0 :
 209                                 (pdimm->package_3ds > 0x1 ? 0x1 :
 210                                  (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
 211                if (pdimm->package_3ds || pdimm->n_ranks != 4)
 212                        pdimm->rcw[13] = 0xc;
 213                else
 214                        pdimm->rcw[13] = 0xd;   /* Fix encoded by board */
 215
 216                break;
 217
 218        case DDR4_SPD_MODULETYPE_UDIMM:
 219        case DDR4_SPD_MODULETYPE_SO_DIMM:
 220                /* Unbuffered DIMMs */
 221                if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 222                        pdimm->mirrored_dimm = 1;
 223                if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
 224                    (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
 225                        /* Fix SPD error found on DIMMs with raw card E0 */
 226                        for (i = 0; i < 18; i++) {
 227                                if (spd->mapping[i] == udimm_rc_e_dq[i])
 228                                        continue;
 229                                spd_error = 1;
 230                                debug("SPD byte %d: 0x%x, should be 0x%x\n",
 231                                      60 + i, spd->mapping[i],
 232                                      udimm_rc_e_dq[i]);
 233                                ptr = (u8 *)&spd->mapping[i];
 234                                *ptr = udimm_rc_e_dq[i];
 235                        }
 236                        if (spd_error)
 237                                puts("SPD DQ mapping error fixed\n");
 238                }
 239                break;
 240
 241        default:
 242                printf("unknown module_type 0x%02X\n", spd->module_type);
 243                return 1;
 244        }
 245
 246        /* SDRAM device parameters */
 247        pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
 248        pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
 249        pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
 250        pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
 251
 252        /*
 253         * The SPD spec has not the ECC bit,
 254         * We consider the DIMM as ECC capability
 255         * when the extension bus exist
 256         */
 257        if (pdimm->ec_sdram_width)
 258                pdimm->edc_config = 0x02;
 259        else
 260                pdimm->edc_config = 0x00;
 261
 262        /*
 263         * The SPD spec has not the burst length byte
 264         * but DDR4 spec has nature BL8 and BC4,
 265         * BL8 -bit3, BC4 -bit2
 266         */
 267        pdimm->burst_lengths_bitmask = 0x0c;
 268
 269        /* MTB - medium timebase
 270         * The MTB in the SPD spec is 125ps,
 271         *
 272         * FTB - fine timebase
 273         * use 1/10th of ps as our unit to avoid floating point
 274         * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
 275         */
 276        if ((spd->timebases & 0xf) == 0x0) {
 277                pdimm->mtb_ps = 125;
 278                pdimm->ftb_10th_ps = 10;
 279
 280        } else {
 281                printf("Unknown Timebases\n");
 282        }
 283
 284        /* sdram minimum cycle time */
 285        pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
 286
 287        /* sdram max cycle time */
 288        pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
 289
 290        /*
 291         * CAS latency supported
 292         * bit0 - CL7
 293         * bit4 - CL11
 294         * bit8 - CL15
 295         * bit12- CL19
 296         * bit16- CL23
 297         */
 298        pdimm->caslat_x  = (spd->caslat_b1 << 7)        |
 299                           (spd->caslat_b2 << 15)       |
 300                           (spd->caslat_b3 << 23);
 301
 302        BUG_ON(spd->caslat_b4 != 0);
 303
 304        /*
 305         * min CAS latency time
 306         */
 307        pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
 308
 309        /*
 310         * min RAS to CAS delay time
 311         */
 312        pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
 313
 314        /*
 315         * Min Row Precharge Delay Time
 316         */
 317        pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
 318
 319        /* min active to precharge delay time */
 320        pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
 321                          spd->tras_min_lsb) * pdimm->mtb_ps;
 322
 323        /* min active to actice/refresh delay time */
 324        pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
 325                                   spd->trc_min_lsb), spd->fine_trc_min);
 326        /* Min Refresh Recovery Delay Time */
 327        pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
 328                       pdimm->mtb_ps;
 329        pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
 330                       pdimm->mtb_ps;
 331        pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
 332                        pdimm->mtb_ps;
 333        /* min four active window delay time */
 334        pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
 335                        pdimm->mtb_ps;
 336
 337        /* min row active to row active delay time, different bank group */
 338        pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
 339        /* min row active to row active delay time, same bank group */
 340        pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
 341        /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
 342        pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
 343
 344        if (pdimm->package_3ds) {
 345                if (pdimm->die_density <= 0x4) {
 346                        pdimm->trfc_slr_ps = 260000;
 347                } else if (pdimm->die_density <= 0x5) {
 348                        pdimm->trfc_slr_ps = 350000;
 349                } else {
 350                        printf("WARN: Unsupported logical rank density 0x%x\n",
 351                               pdimm->die_density);
 352                }
 353        }
 354
 355        /*
 356         * Average periodic refresh interval
 357         * tREFI = 7.8 us at normal temperature range
 358         */
 359        pdimm->refresh_rate_ps = 7800000;
 360
 361        for (i = 0; i < 18; i++)
 362                pdimm->dq_mapping[i] = spd->mapping[i];
 363
 364        pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
 365
 366        return 0;
 367}
 368