1
2
3
4
5
6
7
8
9
10#include <common.h>
11#include <dm.h>
12#include <log.h>
13#include <asm/gpio.h>
14#include <asm/io.h>
15#include <errno.h>
16#include <clk.h>
17#include <dm/device_compat.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20
21#define MSCC_SGPIOS_PER_BANK 32
22#define MSCC_SGPIO_BANK_DEPTH 4
23
24enum {
25 REG_INPUT_DATA,
26 REG_PORT_CONFIG,
27 REG_PORT_ENABLE,
28 REG_SIO_CONFIG,
29 REG_SIO_CLOCK,
30 MAXREG
31};
32
33struct mscc_sgpio_bf {
34 u8 beg;
35 u8 end;
36};
37
38struct mscc_sgpio_props {
39 u8 regoff[MAXREG];
40 struct mscc_sgpio_bf auto_repeat;
41 struct mscc_sgpio_bf port_width;
42 struct mscc_sgpio_bf clk_freq;
43 struct mscc_sgpio_bf bit_source;
44};
45
46#define __M(bf) GENMASK((bf).end, (bf).beg)
47#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
48#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
49
50#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
51#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
52#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
53#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
54#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
55#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
56#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
57
58const struct mscc_sgpio_props props_luton = {
59 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
60 .auto_repeat = { 5, 5 },
61 .port_width = { 2, 3 },
62 .clk_freq = { 0, 11 },
63 .bit_source = { 0, 11 },
64};
65
66const struct mscc_sgpio_props props_ocelot = {
67 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
68 .auto_repeat = { 10, 10 },
69 .port_width = { 7, 8 },
70 .clk_freq = { 8, 19 },
71 .bit_source = { 12, 23 },
72};
73
74struct mscc_sgpio_priv {
75 u32 bitcount;
76 u32 ports;
77 u32 clock;
78 u32 mode[MSCC_SGPIOS_PER_BANK];
79 u32 __iomem *regs;
80 const struct mscc_sgpio_props *props;
81};
82
83static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
84{
85 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
86
87 return readl(reg);
88}
89
90static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
91 u32 val, u32 rno, u32 off)
92{
93 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
94
95 writel(val, reg);
96}
97
98static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
99 u32 rno, u32 off, u32 clear, u32 set)
100{
101 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
102
103 clrsetbits_le32(reg, clear, set);
104}
105
106static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
107{
108 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
109
110 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
111 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
112
113 priv->mode[port] |= BIT(bit);
114
115 return 0;
116}
117
118static int mscc_sgpio_direction_output(struct udevice *dev,
119 unsigned int gpio, int value)
120{
121 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
122 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
123 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
124 u32 mask = 3 << (3 * bit);
125
126 debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
127 port, bit, mask, value);
128
129 value = (value & 3) << (3 * bit);
130 sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
131 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
132 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
133 clrbits_le32(&priv->mode[port], BIT(bit));
134
135 return 0;
136}
137
138static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
139{
140 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
141 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
142 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
143 u32 val = priv->mode[port] & BIT(bit);
144
145 if (val)
146 return GPIOF_INPUT;
147 else
148 return GPIOF_OUTPUT;
149}
150
151static int mscc_sgpio_set_value(struct udevice *dev,
152 unsigned int gpio, int value)
153{
154 return mscc_sgpio_direction_output(dev, gpio, value);
155}
156
157static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
158{
159 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
160 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
161 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
162 int ret;
163
164 if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
165 ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
166 } else {
167 u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
168
169 ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
170 ret = !!(ret & (3 << (3 * bit)));
171 }
172
173 debug("get: gpio %d, port %d, bit %d, value %d\n",
174 gpio, port, bit, ret);
175 return ret;
176}
177
178static int mscc_sgpio_get_count(struct udevice *dev)
179{
180 struct ofnode_phandle_args args;
181 int count = 0, i = 0, ret;
182
183 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
184 while (ret != -ENOENT) {
185 count += args.args[2];
186 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
187 ++i, &args);
188 }
189 return count;
190}
191
192static int mscc_sgpio_probe(struct udevice *dev)
193{
194 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
195 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
196 int err, div_clock = 0, port;
197 u32 val;
198 struct clk clk;
199
200 err = clk_get_by_index(dev, 0, &clk);
201 if (!err) {
202 err = clk_get_rate(&clk);
203 if (IS_ERR_VALUE(err)) {
204 dev_err(dev, "Invalid clk rate\n");
205 return -EINVAL;
206 }
207 div_clock = err;
208 } else {
209 dev_err(dev, "Failed to get clock\n");
210 return err;
211 }
212
213 priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
214 priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
215 priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
216 12500000);
217 if (priv->clock <= 0 || priv->clock > div_clock) {
218 dev_err(dev, "Invalid frequency %d\n", priv->clock);
219 return -EINVAL;
220 }
221
222 uc_priv->gpio_count = mscc_sgpio_get_count(dev);
223 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
224 uc_priv->gpio_count);
225 if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
226 (4 * MSCC_SGPIOS_PER_BANK)) {
227 dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
228 return -EINVAL;
229 }
230 priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
231 MSCC_SGPIOS_PER_BANK);
232 debug("probe: gpios = %d, bit-count = %d\n",
233 uc_priv->gpio_count, priv->bitcount);
234
235 priv->regs = (u32 __iomem *)dev_read_addr(dev);
236 uc_priv->bank_name = "sgpio";
237
238 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
239 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
240 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
241 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
242 val = div_clock / priv->clock;
243 debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
244 div_clock / 1000, priv->clock / 1000, val);
245 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
246 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
247 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
248
249 for (port = 0; port < 32; port++)
250 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
251 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
252
253 debug("probe: sgpio regs = %p\n", priv->regs);
254
255 return 0;
256}
257
258static const struct dm_gpio_ops mscc_sgpio_ops = {
259 .direction_input = mscc_sgpio_direction_input,
260 .direction_output = mscc_sgpio_direction_output,
261 .get_function = mscc_sgpio_get_function,
262 .get_value = mscc_sgpio_get_value,
263 .set_value = mscc_sgpio_set_value,
264};
265
266static const struct udevice_id mscc_sgpio_ids[] = {
267 { .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
268 { .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
269 { }
270};
271
272U_BOOT_DRIVER(gpio_mscc_sgpio) = {
273 .name = "mscc-sgpio",
274 .id = UCLASS_GPIO,
275 .of_match = mscc_sgpio_ids,
276 .ops = &mscc_sgpio_ops,
277 .probe = mscc_sgpio_probe,
278 .priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),
279};
280
