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8#include <common.h>
9#include <command.h>
10#include <console.h>
11#include <linux/delay.h>
12
13#include <dm.h>
14#include <dm/lists.h>
15
16#include <net.h>
17#include <phy.h>
18#include <errno.h>
19#include <miiphy.h>
20#include <malloc.h>
21#include <asm/ti-common/keystone_nav.h>
22#include <asm/ti-common/keystone_net.h>
23#include <asm/ti-common/keystone_serdes.h>
24#include <asm/arch/psc_defs.h>
25#include <linux/libfdt.h>
26
27#include "cpsw_mdio.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#ifdef KEYSTONE2_EMAC_GIG_ENABLE
32#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
33#else
34#define emac_gigabit_enable(x)
35#endif
36
37#define RX_BUFF_NUMS 24
38#define RX_BUFF_LEN 1520
39#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
40#define SGMII_ANEG_TIMEOUT 4000
41
42static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
43
44enum link_type {
45 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
46 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
47 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
48 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
49 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
50 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
51 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
52 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
53 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
54 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
55};
56
57#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
58 ((mac)[2] << 16) | ((mac)[3] << 24))
59#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
60
61#ifdef CONFIG_KSNET_NETCP_V1_0
62
63#define EMAC_EMACSW_BASE_OFS 0x90800
64#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
65
66
67#define CPGMACSL_REG_SA_LO 0x10
68#define CPGMACSL_REG_SA_HI 0x14
69
70#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
71 (x) * 0x30)
72
73#elif defined(CONFIG_KSNET_NETCP_V1_5)
74
75#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
76
77
78#define CPGMACSL_REG_SA_LO 0x308
79#define CPGMACSL_REG_SA_HI 0x30c
80
81#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
82 (x) * 0x1000)
83
84#endif
85
86
87struct ks2_eth_priv {
88 struct udevice *dev;
89 struct phy_device *phydev;
90 struct mii_dev *mdio_bus;
91 int phy_addr;
92 phy_interface_t phy_if;
93 int phy_of_handle;
94 int sgmii_link_type;
95 void *mdio_base;
96 struct rx_buff_desc net_rx_buffs;
97 struct pktdma_cfg *netcp_pktdma;
98 void *hd;
99 int slave_port;
100 enum link_type link_type;
101 bool emac_open;
102 bool has_mdio;
103};
104
105static void __attribute__((unused))
106 keystone2_eth_gigabit_enable(struct udevice *dev)
107{
108 struct ks2_eth_priv *priv = dev_get_priv(dev);
109
110
111
112
113
114 if (priv->has_mdio) {
115 if (priv->phydev->speed != 1000)
116 return;
117 }
118
119 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
120 CPGMACSL_REG_CTL) |
121 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
122 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
123}
124
125#ifdef CONFIG_SOC_K2G
126int keystone_rgmii_config(struct phy_device *phy_dev)
127{
128 unsigned int i, status;
129
130 i = 0;
131 do {
132 if (i > SGMII_ANEG_TIMEOUT) {
133 puts(" TIMEOUT !\n");
134 phy_dev->link = 0;
135 return 0;
136 }
137
138 if (ctrlc()) {
139 puts("user interrupt!\n");
140 phy_dev->link = 0;
141 return -EINTR;
142 }
143
144 if ((i++ % 500) == 0)
145 printf(".");
146
147 udelay(1000);
148 status = readl(RGMII_STATUS_REG);
149 } while (!(status & RGMII_REG_STATUS_LINK));
150
151 puts(" done\n");
152
153 return 0;
154}
155#else
156int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
157{
158 unsigned int i, status, mask;
159 unsigned int mr_adv_ability, control;
160
161 switch (interface) {
162 case SGMII_LINK_MAC_MAC_AUTONEG:
163 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
164 SGMII_REG_MR_ADV_LINK |
165 SGMII_REG_MR_ADV_FULL_DUPLEX |
166 SGMII_REG_MR_ADV_GIG_MODE);
167 control = (SGMII_REG_CONTROL_MASTER |
168 SGMII_REG_CONTROL_AUTONEG);
169
170 break;
171 case SGMII_LINK_MAC_PHY:
172 case SGMII_LINK_MAC_PHY_FORCED:
173 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
174 control = SGMII_REG_CONTROL_AUTONEG;
175
176 break;
177 case SGMII_LINK_MAC_MAC_FORCED:
178 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
179 SGMII_REG_MR_ADV_LINK |
180 SGMII_REG_MR_ADV_FULL_DUPLEX |
181 SGMII_REG_MR_ADV_GIG_MODE);
182 control = SGMII_REG_CONTROL_MASTER;
183
184 break;
185 case SGMII_LINK_MAC_FIBER:
186 mr_adv_ability = 0x20;
187 control = SGMII_REG_CONTROL_AUTONEG;
188
189 break;
190 default:
191 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
192 control = SGMII_REG_CONTROL_AUTONEG;
193 }
194
195 __raw_writel(0, SGMII_CTL_REG(port));
196
197
198
199
200
201 for (i = 0; i < 1000; i++) {
202 udelay(2000);
203 status = __raw_readl(SGMII_STATUS_REG(port));
204 if ((status & SGMII_REG_STATUS_LOCK) != 0)
205 break;
206 }
207
208 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
209 __raw_writel(control, SGMII_CTL_REG(port));
210
211
212 mask = SGMII_REG_STATUS_LINK;
213
214 if (control & SGMII_REG_CONTROL_AUTONEG)
215 mask |= SGMII_REG_STATUS_AUTONEG;
216
217 status = __raw_readl(SGMII_STATUS_REG(port));
218 if ((status & mask) == mask)
219 return 0;
220
221 printf("\n%s Waiting for SGMII auto negotiation to complete",
222 phy_dev->dev->name);
223 while ((status & mask) != mask) {
224
225
226
227 if (i > SGMII_ANEG_TIMEOUT) {
228 puts(" TIMEOUT !\n");
229 phy_dev->link = 0;
230 return 0;
231 }
232
233 if (ctrlc()) {
234 puts("user interrupt!\n");
235 phy_dev->link = 0;
236 return -EINTR;
237 }
238
239 if ((i++ % 500) == 0)
240 printf(".");
241
242 udelay(1000);
243 status = __raw_readl(SGMII_STATUS_REG(port));
244 }
245 puts(" done\n");
246
247 return 0;
248}
249#endif
250
251int mac_sl_reset(u32 port)
252{
253 u32 i, v;
254
255 if (port >= DEVICE_N_GMACSL_PORTS)
256 return GMACSL_RET_INVALID_PORT;
257
258
259 writel(CPGMAC_REG_RESET_VAL_RESET,
260 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
261
262
263 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
264 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
265 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
266 CPGMAC_REG_RESET_VAL_RESET)
267 return GMACSL_RET_OK;
268 }
269
270
271 return GMACSL_RET_WARN_RESET_INCOMPLETE;
272}
273
274int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
275{
276 u32 v, i;
277 int ret = GMACSL_RET_OK;
278
279 if (port >= DEVICE_N_GMACSL_PORTS)
280 return GMACSL_RET_INVALID_PORT;
281
282 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
283 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
284 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
285 }
286
287
288 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
289 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
290 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
291 CPGMAC_REG_RESET_VAL_RESET)
292 break;
293 }
294
295 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
296 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
297
298 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
299 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
300
301#ifndef CONFIG_SOC_K2HK
302
303 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
304#endif
305
306 return ret;
307}
308
309int ethss_config(u32 ctl, u32 max_pkt_size)
310{
311 u32 i;
312
313
314 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
315
316
317 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
318
319
320 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
321 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
322
323
324 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
325 CPSW_REG_VAL_ALE_CTL_BYPASS,
326 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
327
328
329 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
330 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
331 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
332
333 return 0;
334}
335
336int ethss_start(void)
337{
338 int i;
339 struct mac_sl_cfg cfg;
340
341 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
342 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
343
344 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
345 mac_sl_reset(i);
346 mac_sl_config(i, &cfg);
347 }
348
349 return 0;
350}
351
352int ethss_stop(void)
353{
354 int i;
355
356 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
357 mac_sl_reset(i);
358
359 return 0;
360}
361
362struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
363 .clk = SERDES_CLOCK_156P25M,
364 .rate = SERDES_RATE_5G,
365 .rate_mode = SERDES_QUARTER_RATE,
366 .intf = SERDES_PHY_SGMII,
367 .loopback = 0,
368};
369
370#ifndef CONFIG_SOC_K2G
371static void keystone2_net_serdes_setup(void)
372{
373 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
374 &ks2_serdes_sgmii_156p25mhz,
375 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
376
377#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
378 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
379 &ks2_serdes_sgmii_156p25mhz,
380 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
381#endif
382
383
384 udelay(5000);
385}
386#endif
387
388static int ks2_eth_start(struct udevice *dev)
389{
390 struct ks2_eth_priv *priv = dev_get_priv(dev);
391
392#ifdef CONFIG_SOC_K2G
393 keystone_rgmii_config(priv->phydev);
394#else
395 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
396 priv->sgmii_link_type);
397#endif
398
399 udelay(10000);
400
401
402 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
403
404 qm_init();
405
406 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
407 pr_err("ksnav_init failed\n");
408 goto err_knav_init;
409 }
410
411
412
413
414
415
416 hw_config_streaming_switch();
417
418 if (priv->has_mdio) {
419 phy_startup(priv->phydev);
420 if (priv->phydev->link == 0) {
421 pr_err("phy startup failed\n");
422 goto err_phy_start;
423 }
424 }
425
426 emac_gigabit_enable(dev);
427
428 ethss_start();
429
430 priv->emac_open = true;
431
432 return 0;
433
434err_phy_start:
435 ksnav_close(priv->netcp_pktdma);
436err_knav_init:
437 qm_close();
438
439 return -EFAULT;
440}
441
442static int ks2_eth_send(struct udevice *dev, void *packet, int length)
443{
444 struct ks2_eth_priv *priv = dev_get_priv(dev);
445
446 genphy_update_link(priv->phydev);
447 if (priv->phydev->link == 0)
448 return -1;
449
450 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
451 length = EMAC_MIN_ETHERNET_PKT_SIZE;
452
453 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
454 length, (priv->slave_port) << 16);
455}
456
457static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
458{
459 struct ks2_eth_priv *priv = dev_get_priv(dev);
460 int pkt_size;
461 u32 *pkt = NULL;
462
463 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
464 if (priv->hd == NULL)
465 return -EAGAIN;
466
467 *packetp = (uchar *)pkt;
468
469 return pkt_size;
470}
471
472static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
473 int length)
474{
475 struct ks2_eth_priv *priv = dev_get_priv(dev);
476
477 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
478
479 return 0;
480}
481
482static void ks2_eth_stop(struct udevice *dev)
483{
484 struct ks2_eth_priv *priv = dev_get_priv(dev);
485
486 if (!priv->emac_open)
487 return;
488 ethss_stop();
489
490 ksnav_close(priv->netcp_pktdma);
491 qm_close();
492 phy_shutdown(priv->phydev);
493 priv->emac_open = false;
494}
495
496int ks2_eth_read_rom_hwaddr(struct udevice *dev)
497{
498 struct ks2_eth_priv *priv = dev_get_priv(dev);
499 struct eth_pdata *pdata = dev_get_platdata(dev);
500 u32 maca = 0;
501 u32 macb = 0;
502
503
504 if (priv->slave_port == 1) {
505 maca = __raw_readl(MAC_ID_BASE_ADDR);
506 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
507 }
508
509 pdata->enetaddr[0] = (macb >> 8) & 0xff;
510 pdata->enetaddr[1] = (macb >> 0) & 0xff;
511 pdata->enetaddr[2] = (maca >> 24) & 0xff;
512 pdata->enetaddr[3] = (maca >> 16) & 0xff;
513 pdata->enetaddr[4] = (maca >> 8) & 0xff;
514 pdata->enetaddr[5] = (maca >> 0) & 0xff;
515
516 return 0;
517}
518
519int ks2_eth_write_hwaddr(struct udevice *dev)
520{
521 struct ks2_eth_priv *priv = dev_get_priv(dev);
522 struct eth_pdata *pdata = dev_get_platdata(dev);
523
524 writel(mac_hi(pdata->enetaddr),
525 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
526 CPGMACSL_REG_SA_HI);
527 writel(mac_lo(pdata->enetaddr),
528 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
529 CPGMACSL_REG_SA_LO);
530
531 return 0;
532}
533
534static int ks2_eth_probe(struct udevice *dev)
535{
536 struct ks2_eth_priv *priv = dev_get_priv(dev);
537 struct mii_dev *mdio_bus;
538
539 priv->dev = dev;
540 priv->emac_open = false;
541
542
543 if (cpu_is_k2g())
544 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
545
546
547#ifndef CONFIG_SOC_K2G
548 if (psc_enable_module(KS2_LPSC_PA))
549 return -EACCES;
550#endif
551 if (psc_enable_module(KS2_LPSC_CPGMAC))
552 return -EACCES;
553 if (psc_enable_module(KS2_LPSC_CRYPTO))
554 return -EACCES;
555
556 if (cpu_is_k2e() || cpu_is_k2l())
557 pll_pa_clk_sel();
558
559 priv->net_rx_buffs.buff_ptr = rx_buffs;
560 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
561 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
562
563 if (priv->slave_port == 1) {
564#ifndef CONFIG_SOC_K2G
565 keystone2_net_serdes_setup();
566#endif
567
568
569
570
571 mdio_bus = cpsw_mdio_init("ethernet-mdio",
572 (u32)priv->mdio_base,
573 EMAC_MDIO_CLOCK_FREQ,
574 EMAC_MDIO_BUS_FREQ);
575 if (!mdio_bus) {
576 pr_err("MDIO alloc failed\n");
577 return -ENOMEM;
578 }
579 priv->mdio_bus = mdio_bus;
580 } else {
581
582 struct ks2_eth_priv *parent_priv;
583
584 parent_priv = dev_get_priv(dev->parent);
585 priv->mdio_bus = parent_priv->mdio_bus;
586 priv->mdio_base = parent_priv->mdio_base;
587 }
588
589 priv->netcp_pktdma = &netcp_pktdma;
590
591 if (priv->has_mdio) {
592 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
593 dev, priv->phy_if);
594#ifdef CONFIG_DM_ETH
595 if (priv->phy_of_handle)
596 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
597#endif
598 phy_config(priv->phydev);
599 }
600
601 return 0;
602}
603
604int ks2_eth_remove(struct udevice *dev)
605{
606 struct ks2_eth_priv *priv = dev_get_priv(dev);
607
608 cpsw_mdio_free(priv->mdio_bus);
609
610 return 0;
611}
612
613static const struct eth_ops ks2_eth_ops = {
614 .start = ks2_eth_start,
615 .send = ks2_eth_send,
616 .recv = ks2_eth_recv,
617 .free_pkt = ks2_eth_free_pkt,
618 .stop = ks2_eth_stop,
619 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
620 .write_hwaddr = ks2_eth_write_hwaddr,
621};
622
623static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
624{
625 const void *fdt = gd->fdt_blob;
626 struct udevice *sl_dev;
627 int interfaces;
628 int sec_slave;
629 int slave;
630 int ret;
631 char *slave_name;
632
633 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
634 fdt_for_each_subnode(slave, fdt, interfaces) {
635 int slave_no;
636
637 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
638 if (slave_no == -ENOENT)
639 continue;
640
641 if (slave_no == 0) {
642
643 *gbe_0 = slave;
644 } else {
645
646 slave_name = malloc(20);
647 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
648 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
649 slave_name, offset_to_ofnode(slave),
650 &sl_dev);
651 if (ret) {
652 pr_err("ks2_net - not able to bind slave interfaces\n");
653 return ret;
654 }
655 }
656 }
657
658 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
659 fdt_for_each_subnode(slave, fdt, sec_slave) {
660 int slave_no;
661
662 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
663 if (slave_no == -ENOENT)
664 continue;
665
666
667 slave_name = malloc(20);
668 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
669 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
670 offset_to_ofnode(slave), &sl_dev);
671 if (ret) {
672 pr_err("ks2_net - not able to bind slave interfaces\n");
673 return ret;
674 }
675 }
676
677 return 0;
678}
679
680static int ks2_eth_parse_slave_interface(int netcp, int slave,
681 struct ks2_eth_priv *priv,
682 struct eth_pdata *pdata)
683{
684 const void *fdt = gd->fdt_blob;
685 int mdio;
686 int phy;
687 int dma_count;
688 u32 dma_channel[8];
689 const char *phy_mode;
690
691 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
692 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
693
694
695 priv->slave_port += 1;
696
697 dma_count = fdtdec_get_int_array_count(fdt, netcp,
698 "ti,navigator-dmas",
699 dma_channel, 8);
700
701 if (dma_count > (2 * priv->slave_port)) {
702 int dma_idx;
703
704 dma_idx = priv->slave_port * 2 - 1;
705 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
706 }
707
708 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
709
710 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
711
712 if (phy >= 0) {
713 priv->phy_of_handle = phy;
714 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
715
716 mdio = fdt_parent_offset(fdt, phy);
717 if (mdio < 0) {
718 pr_err("mdio dt not found\n");
719 return -ENODEV;
720 }
721 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
722 }
723
724 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
725 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
726 pdata->phy_interface = priv->phy_if;
727 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
728 priv->has_mdio = true;
729 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
730 phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
731 if (phy_mode) {
732 priv->phy_if = phy_get_interface_by_name(phy_mode);
733 if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
734 priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
735 priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
736 priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
737 pr_err("invalid phy-mode\n");
738 return -EINVAL;
739 }
740 } else {
741 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
742 }
743 pdata->phy_interface = priv->phy_if;
744 priv->has_mdio = true;
745 }
746
747 return 0;
748}
749
750static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
751{
752 struct ks2_eth_priv *priv = dev_get_priv(dev);
753 struct eth_pdata *pdata = dev_get_platdata(dev);
754 const void *fdt = gd->fdt_blob;
755 int slave = dev_of_offset(dev);
756 int interfaces;
757 int gbe;
758 int netcp_devices;
759 int netcp;
760
761 interfaces = fdt_parent_offset(fdt, slave);
762 gbe = fdt_parent_offset(fdt, interfaces);
763 netcp_devices = fdt_parent_offset(fdt, gbe);
764 netcp = fdt_parent_offset(fdt, netcp_devices);
765
766 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
767
768 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
769
770 return 0;
771}
772
773static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
774{
775 struct ks2_eth_priv *priv = dev_get_priv(dev);
776 struct eth_pdata *pdata = dev_get_platdata(dev);
777 const void *fdt = gd->fdt_blob;
778 int gbe_0 = -ENODEV;
779 int netcp_devices;
780 int gbe;
781
782 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
783 "netcp-devices");
784 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
785
786 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
787
788 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
789
790 pdata->iobase = devfdt_get_addr(dev);
791
792 return 0;
793}
794
795static const struct udevice_id ks2_eth_ids[] = {
796 { .compatible = "ti,netcp-1.0" },
797 { }
798};
799
800U_BOOT_DRIVER(eth_ks2_slave) = {
801 .name = "eth_ks2_sl",
802 .id = UCLASS_ETH,
803 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
804 .probe = ks2_eth_probe,
805 .remove = ks2_eth_remove,
806 .ops = &ks2_eth_ops,
807 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
808 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
809 .flags = DM_FLAG_ALLOC_PRIV_DMA,
810};
811
812U_BOOT_DRIVER(eth_ks2) = {
813 .name = "eth_ks2",
814 .id = UCLASS_ETH,
815 .of_match = ks2_eth_ids,
816 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
817 .probe = ks2_eth_probe,
818 .remove = ks2_eth_remove,
819 .ops = &ks2_eth_ops,
820 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
821 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
822 .flags = DM_FLAG_ALLOC_PRIV_DMA,
823};
824
