uboot/drivers/phy/phy-ti-am654.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/**
   3 * PCIe SERDES driver for AM654x SoC
   4 *
   5 * Copyright (C) 2018 Texas Instruments
   6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7 */
   8
   9#include <common.h>
  10#include <clk-uclass.h>
  11#include <dm.h>
  12#include <log.h>
  13#include <dm/device.h>
  14#include <dm/device_compat.h>
  15#include <dm/lists.h>
  16#include <dt-bindings/phy/phy.h>
  17#include <generic-phy.h>
  18#include <asm/io.h>
  19#include <asm/arch/sys_proto.h>
  20#include <power-domain.h>
  21#include <regmap.h>
  22#include <syscon.h>
  23#include <linux/bitops.h>
  24#include <linux/delay.h>
  25#include <linux/err.h>
  26
  27#define CMU_R07C                0x7c
  28#define CMU_MASTER_CDN_O        BIT(24)
  29
  30#define COMLANE_R138            0xb38
  31#define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
  32#define CONFIG_VERSION_REG_SHIFT 16
  33#define VERSION                 0x70
  34
  35#define COMLANE_R190            0xb90
  36#define L1_MASTER_CDN_O         BIT(9)
  37
  38#define COMLANE_R194            0xb94
  39#define CMU_OK_I_0              BIT(19)
  40
  41#define SERDES_CTRL             0x1fd0
  42#define POR_EN                  BIT(29)
  43
  44#define WIZ_LANEXCTL_STS        0x1fe0
  45#define TX0_ENABLE_OVL          BIT(31)
  46#define TX0_ENABLE_MASK         GENMASK(30, 29)
  47#define TX0_ENABLE_SHIFT        29
  48#define TX0_DISABLE_STATE       0x0
  49#define TX0_SLEEP_STATE         0x1
  50#define TX0_SNOOZE_STATE        0x2
  51#define TX0_ENABLE_STATE        0x3
  52#define RX0_ENABLE_OVL          BIT(15)
  53#define RX0_ENABLE_MASK         GENMASK(14, 13)
  54#define RX0_ENABLE_SHIFT        13
  55#define RX0_DISABLE_STATE       0x0
  56#define RX0_SLEEP_STATE         0x1
  57#define RX0_SNOOZE_STATE        0x2
  58#define RX0_ENABLE_STATE        0x3
  59
  60#define WIZ_PLL_CTRL            0x1ff4
  61#define PLL_ENABLE_OVL          BIT(31)
  62#define PLL_ENABLE_MASK         GENMASK(30, 29)
  63#define PLL_ENABLE_SHIFT        29
  64#define PLL_DISABLE_STATE       0x0
  65#define PLL_SLEEP_STATE         0x1
  66#define PLL_SNOOZE_STATE        0x2
  67#define PLL_ENABLE_STATE        0x3
  68#define PLL_OK                  BIT(28)
  69
  70#define PLL_LOCK_TIME           1000    /* in milliseconds */
  71#define SLEEP_TIME              100     /* in microseconds */
  72
  73#define LANE_USB3               0x0
  74#define LANE_PCIE0_LANE0        0x1
  75
  76#define LANE_PCIE1_LANE0        0x0
  77#define LANE_PCIE0_LANE1        0x1
  78
  79#define SERDES_NUM_CLOCKS       3
  80
  81/* SERDES control MMR bit offsets */
  82#define SERDES_CTL_LANE_FUNC_SEL_SHIFT  0
  83#define SERDES_CTL_LANE_FUNC_SEL_MASK   GENMASK(1, 0)
  84#define SERDES_CTL_CLK_SEL_SHIFT        4
  85#define SERDES_CTL_CLK_SEL_MASK         GENMASK(7, 4)
  86
  87/**
  88 * struct serdes_am654_mux_clk_data - clock controller information structure
  89 */
  90struct serdes_am654_mux_clk_data {
  91        struct regmap *regmap;
  92        struct clk_bulk parents;
  93};
  94
  95static int serdes_am654_mux_clk_probe(struct udevice *dev)
  96{
  97        struct serdes_am654_mux_clk_data *data = dev_get_priv(dev);
  98        struct udevice *syscon;
  99        struct regmap *regmap;
 100        int ret;
 101
 102        debug("%s(dev=%s)\n", __func__, dev->name);
 103
 104        if (!data)
 105                return -ENOMEM;
 106
 107        ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 108                                           "ti,serdes-clk", &syscon);
 109        if (ret) {
 110                dev_err(dev, "unable to find syscon device\n");
 111                return ret;
 112        }
 113
 114        regmap = syscon_get_regmap(syscon);
 115        if (IS_ERR(regmap)) {
 116                dev_err(dev, "Fail to get Syscon regmap\n");
 117                return PTR_ERR(regmap);
 118        }
 119
 120        data->regmap = regmap;
 121
 122        ret = clk_get_bulk(dev, &data->parents);
 123        if (ret) {
 124                dev_err(dev, "Failed to obtain parent clocks\n");
 125                return ret;
 126        }
 127
 128        return 0;
 129}
 130
 131static int mux_table[SERDES_NUM_CLOCKS][3] = {
 132        /*
 133         * The entries represent values for selecting between
 134         * {left input, external reference clock, right input}
 135         * Only one of Left Output or Right Output should be used since
 136         * both left and right output clock uses the same bits and modifying
 137         * one clock will impact the other.
 138         */
 139        { BIT(2),               0, BIT(0) }, /* Mux of CMU refclk */
 140        {     -1,          BIT(3), BIT(1) }, /* Mux of Left Output */
 141        { BIT(1), BIT(3) | BIT(1),     -1 }, /* Mux of Right Output */
 142};
 143
 144static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)
 145{
 146        struct serdes_am654_mux_clk_data *data = dev_get_priv(clk->dev);
 147        u32 val;
 148        int i;
 149
 150        debug("%s(clk=%s, parent=%s)\n", __func__, clk->dev->name,
 151              parent->dev->name);
 152
 153        /*
 154         * Since we have the same device-tree node represent both the
 155         * clock and serdes device, we have two devices associated with
 156         * the serdes node. assigned-clocks for this node is processed twice,
 157         * once for the clock device and another time for the serdes
 158         * device. When it is processed for the clock device, it is before
 159         * the probe for clock device has been called. We ignore this case
 160         * and rely on assigned-clocks to be processed correctly for the
 161         * serdes case.
 162         */
 163        if (!data->regmap)
 164                return 0;
 165
 166        for (i = 0; i < data->parents.count; i++) {
 167                if (clk_is_match(&data->parents.clks[i], parent))
 168                        break;
 169        }
 170
 171        if (i >= data->parents.count)
 172                return -EINVAL;
 173
 174        val = mux_table[clk->id][i];
 175        val <<= SERDES_CTL_CLK_SEL_SHIFT;
 176
 177        regmap_update_bits(data->regmap, 0, SERDES_CTL_CLK_SEL_MASK, val);
 178
 179        return 0;
 180}
 181
 182static struct clk_ops serdes_am654_mux_clk_ops = {
 183        .set_parent = serdes_am654_mux_clk_set_parent,
 184};
 185
 186U_BOOT_DRIVER(serdes_am654_mux_clk) = {
 187        .name = "ti-serdes-am654-mux-clk",
 188        .id = UCLASS_CLK,
 189        .probe = serdes_am654_mux_clk_probe,
 190        .priv_auto_alloc_size = sizeof(struct serdes_am654_mux_clk_data),
 191        .ops = &serdes_am654_mux_clk_ops,
 192};
 193
 194struct serdes_am654 {
 195        struct regmap *regmap;
 196        struct regmap *serdes_ctl;
 197};
 198
 199static int serdes_am654_enable_pll(struct serdes_am654 *phy)
 200{
 201        u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
 202        u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT);
 203
 204        regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val);
 205
 206        return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val,
 207                                        val & PLL_OK, 1000, PLL_LOCK_TIME);
 208}
 209
 210static void serdes_am654_disable_pll(struct serdes_am654 *phy)
 211{
 212        u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
 213
 214        regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0);
 215}
 216
 217static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
 218{
 219        u32 mask;
 220        u32 val;
 221
 222        /* Enable TX */
 223        mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
 224        val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT);
 225        regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
 226
 227        /* Enable RX */
 228        mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
 229        val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT);
 230        regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
 231
 232        return 0;
 233}
 234
 235static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
 236{
 237        u32 mask;
 238
 239        /* Disable TX */
 240        mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
 241        regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
 242
 243        /* Disable RX */
 244        mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
 245        regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
 246
 247        return 0;
 248}
 249
 250static int serdes_am654_power_on(struct phy *x)
 251{
 252        struct serdes_am654 *phy = dev_get_priv(x->dev);
 253        int ret;
 254        u32 val;
 255
 256        ret = serdes_am654_enable_pll(phy);
 257        if (ret) {
 258                dev_err(x->dev, "Failed to enable PLL\n");
 259                return ret;
 260        }
 261
 262        ret = serdes_am654_enable_txrx(phy);
 263        if (ret) {
 264                dev_err(x->dev, "Failed to enable TX RX\n");
 265                return ret;
 266        }
 267
 268        return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val,
 269                                        val & CMU_OK_I_0, SLEEP_TIME,
 270                                        PLL_LOCK_TIME);
 271}
 272
 273static int serdes_am654_power_off(struct phy *x)
 274{
 275        struct serdes_am654 *phy = dev_get_priv(x->dev);
 276
 277        serdes_am654_disable_txrx(phy);
 278        serdes_am654_disable_pll(phy);
 279
 280        return 0;
 281}
 282
 283static int serdes_am654_init(struct phy *x)
 284{
 285        struct serdes_am654 *phy = dev_get_priv(x->dev);
 286        u32 mask;
 287        u32 val;
 288
 289        mask = CONFIG_VERSION_REG_MASK;
 290        val = VERSION << CONFIG_VERSION_REG_SHIFT;
 291        regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
 292
 293        val = CMU_MASTER_CDN_O;
 294        regmap_update_bits(phy->regmap, CMU_R07C, val, val);
 295
 296        val = L1_MASTER_CDN_O;
 297        regmap_update_bits(phy->regmap, COMLANE_R190, val, val);
 298
 299        return 0;
 300}
 301
 302static int serdes_am654_reset(struct phy *x)
 303{
 304        struct serdes_am654 *phy = dev_get_priv(x->dev);
 305        u32 val;
 306
 307        val = POR_EN;
 308        regmap_update_bits(phy->regmap, SERDES_CTRL, val, val);
 309        mdelay(1);
 310        regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0);
 311
 312        return 0;
 313}
 314
 315static int serdes_am654_of_xlate(struct phy *x,
 316                                 struct ofnode_phandle_args *args)
 317{
 318        struct serdes_am654 *phy = dev_get_priv(x->dev);
 319
 320        if (args->args_count != 2) {
 321                dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
 322                        args->args_count);
 323                return -EINVAL;
 324        }
 325
 326        if (args->args[0] != PHY_TYPE_PCIE) {
 327                dev_err(phy->dev, "Unrecognized PHY type: %d\n",
 328                        args->args[0]);
 329                return -EINVAL;
 330        }
 331
 332        x->id = args->args[0] | (args->args[1] << 16);
 333
 334        /* Setup mux mode using second argument */
 335        regmap_update_bits(phy->serdes_ctl, 0, SERDES_CTL_LANE_FUNC_SEL_MASK,
 336                           args->args[1]);
 337
 338        return 0;
 339}
 340
 341static int serdes_am654_bind(struct udevice *dev)
 342{
 343        int ret;
 344
 345        ret = device_bind_driver_to_node(dev->parent,
 346                                         "ti-serdes-am654-mux-clk",
 347                                         dev_read_name(dev), dev->node,
 348                                         NULL);
 349        if (ret) {
 350                dev_err(dev, "%s: not able to bind clock driver\n", __func__);
 351                return ret;
 352        }
 353
 354        return 0;
 355}
 356
 357static int serdes_am654_probe(struct udevice *dev)
 358{
 359        struct serdes_am654 *phy = dev_get_priv(dev);
 360        struct power_domain serdes_pwrdmn;
 361        struct regmap *serdes_ctl;
 362        struct regmap *map;
 363        int ret;
 364
 365        ret = regmap_init_mem(dev_ofnode(dev), &map);
 366        if (ret)
 367                return ret;
 368
 369        phy->regmap = map;
 370
 371        serdes_ctl = syscon_regmap_lookup_by_phandle(dev, "ti,serdes-clk");
 372        if (IS_ERR(serdes_ctl)) {
 373                dev_err(dev, "unable to find syscon device\n");
 374                return PTR_ERR(serdes_ctl);
 375        }
 376
 377        phy->serdes_ctl = serdes_ctl;
 378
 379        ret = power_domain_get_by_index(dev, &serdes_pwrdmn, 0);
 380        if (ret) {
 381                dev_err(dev, "failed to get power domain\n");
 382                return ret;
 383        }
 384
 385        ret = power_domain_on(&serdes_pwrdmn);
 386        if (ret) {
 387                dev_err(dev, "Power domain on failed\n");
 388                return ret;
 389        }
 390
 391        return 0;
 392}
 393
 394static const struct udevice_id serdes_am654_phy_ids[] = {
 395        {
 396                .compatible = "ti,phy-am654-serdes",
 397        },
 398};
 399
 400static const struct phy_ops serdes_am654_phy_ops = {
 401        .reset          = serdes_am654_reset,
 402        .init           = serdes_am654_init,
 403        .power_on       = serdes_am654_power_on,
 404        .power_off      = serdes_am654_power_off,
 405        .of_xlate       = serdes_am654_of_xlate,
 406};
 407
 408U_BOOT_DRIVER(am654_serdes_phy) = {
 409        .name   = "am654_serdes_phy",
 410        .id     = UCLASS_PHY,
 411        .of_match = serdes_am654_phy_ids,
 412        .bind = serdes_am654_bind,
 413        .ops = &serdes_am654_phy_ops,
 414        .probe = serdes_am654_probe,
 415        .priv_auto_alloc_size = sizeof(struct serdes_am654),
 416};
 417