1#include <common.h>
2#include <dm.h>
3#include <hwspinlock.h>
4#include <log.h>
5#include <malloc.h>
6#include <asm/arch/gpio.h>
7#include <asm/gpio.h>
8#include <asm/io.h>
9#include <dm/device_compat.h>
10#include <dm/lists.h>
11#include <dm/pinctrl.h>
12#include <linux/bitops.h>
13#include <linux/err.h>
14#include <linux/libfdt.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define MAX_PINS_ONE_IP 70
19#define MODE_BITS_MASK 3
20#define OSPEED_MASK 3
21#define PUPD_MASK 3
22#define OTYPE_MSK 1
23#define AFR_MASK 0xF
24
25struct stm32_pinctrl_priv {
26 struct hwspinlock hws;
27 int pinctrl_ngpios;
28 struct list_head gpio_dev;
29};
30
31struct stm32_gpio_bank {
32 struct udevice *gpio_dev;
33 struct list_head list;
34};
35
36#ifndef CONFIG_SPL_BUILD
37
38static char pin_name[PINNAME_SIZE];
39#define PINMUX_MODE_COUNT 5
40static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
41 "gpio input",
42 "gpio output",
43 "analog",
44 "unknown",
45 "alt function",
46};
47
48static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
49{
50 struct stm32_gpio_priv *priv = dev_get_priv(dev);
51 struct stm32_gpio_regs *regs = priv->regs;
52 u32 af;
53 u32 alt_shift = (offset % 8) * 4;
54 u32 alt_index = offset / 8;
55
56 af = (readl(®s->afr[alt_index]) &
57 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
58
59 return af;
60}
61
62static int stm32_populate_gpio_dev_list(struct udevice *dev)
63{
64 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
65 struct udevice *gpio_dev;
66 struct udevice *child;
67 struct stm32_gpio_bank *gpio_bank;
68 int ret;
69
70
71
72
73
74
75
76 list_for_each_entry(child, &dev->child_head, sibling_node) {
77 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
78 &gpio_dev);
79 if (ret < 0)
80 continue;
81
82 gpio_bank = malloc(sizeof(*gpio_bank));
83 if (!gpio_bank) {
84 dev_err(dev, "Not enough memory\n");
85 return -ENOMEM;
86 }
87
88 gpio_bank->gpio_dev = gpio_dev;
89 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
90 }
91
92 return 0;
93}
94
95static int stm32_pinctrl_get_pins_count(struct udevice *dev)
96{
97 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
98 struct gpio_dev_priv *uc_priv;
99 struct stm32_gpio_bank *gpio_bank;
100
101
102
103
104
105 if (priv->pinctrl_ngpios)
106 return priv->pinctrl_ngpios;
107
108 if (list_empty(&priv->gpio_dev))
109 stm32_populate_gpio_dev_list(dev);
110
111
112
113
114 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
115 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
116
117 priv->pinctrl_ngpios += uc_priv->gpio_count;
118 }
119
120 return priv->pinctrl_ngpios;
121}
122
123static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
124 unsigned int selector,
125 unsigned int *idx)
126{
127 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
128 struct stm32_gpio_bank *gpio_bank;
129 struct gpio_dev_priv *uc_priv;
130 int pin_count = 0;
131
132 if (list_empty(&priv->gpio_dev))
133 stm32_populate_gpio_dev_list(dev);
134
135
136 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
137 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
138
139 if (selector < (pin_count + uc_priv->gpio_count)) {
140
141
142
143
144 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
145 selector - pin_count);
146 if (IS_ERR_VALUE(*idx))
147 return NULL;
148
149 return gpio_bank->gpio_dev;
150 }
151 pin_count += uc_priv->gpio_count;
152 }
153
154 return NULL;
155}
156
157static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
158 unsigned int selector)
159{
160 struct gpio_dev_priv *uc_priv;
161 struct udevice *gpio_dev;
162 unsigned int gpio_idx;
163
164
165 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
166 if (!gpio_dev) {
167 snprintf(pin_name, PINNAME_SIZE, "Error");
168 } else {
169 uc_priv = dev_get_uclass_priv(gpio_dev);
170
171 snprintf(pin_name, PINNAME_SIZE, "%s%d",
172 uc_priv->bank_name,
173 gpio_idx);
174 }
175
176 return pin_name;
177}
178
179static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
180 unsigned int selector,
181 char *buf,
182 int size)
183{
184 struct udevice *gpio_dev;
185 const char *label;
186 int mode;
187 int af_num;
188 unsigned int gpio_idx;
189
190
191 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
192
193 if (!gpio_dev)
194 return -ENODEV;
195
196 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
197
198 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
199 selector, gpio_idx, mode);
200
201
202 switch (mode) {
203 case GPIOF_UNKNOWN:
204
205 return -EINVAL;
206 case GPIOF_UNUSED:
207 snprintf(buf, size, "%s", pinmux_mode[mode]);
208 break;
209 case GPIOF_FUNC:
210 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
211 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
212 break;
213 case GPIOF_OUTPUT:
214 case GPIOF_INPUT:
215 snprintf(buf, size, "%s %s",
216 pinmux_mode[mode], label ? label : "");
217 break;
218 }
219
220 return 0;
221}
222
223#endif
224
225static int stm32_pinctrl_probe(struct udevice *dev)
226{
227 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
228 int ret;
229
230 INIT_LIST_HEAD(&priv->gpio_dev);
231
232
233 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
234 if (ret)
235 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
236 __func__, ret);
237
238 return 0;
239}
240
241static int stm32_gpio_config(struct gpio_desc *desc,
242 const struct stm32_gpio_ctl *ctl)
243{
244 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
245 struct stm32_gpio_regs *regs = priv->regs;
246 struct stm32_pinctrl_priv *ctrl_priv;
247 int ret;
248 u32 index;
249
250 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
251 ctl->pupd > 2 || ctl->speed > 3)
252 return -EINVAL;
253
254 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
255 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
256 if (ret == -ETIME) {
257 dev_err(desc->dev, "HWSpinlock timeout\n");
258 return ret;
259 }
260
261 index = (desc->offset & 0x07) * 4;
262 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
263 ctl->af << index);
264
265 index = desc->offset * 2;
266 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
267 ctl->mode << index);
268 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
269 ctl->speed << index);
270 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
271
272 index = desc->offset;
273 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
274
275 hwspinlock_unlock(&ctrl_priv->hws);
276
277 return 0;
278}
279
280static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
281{
282 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
283 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
284 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
285 gpio_dsc->pin);
286
287 return 0;
288}
289
290static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
291{
292 gpio_fn &= 0x00FF;
293 gpio_ctl->af = 0;
294
295 switch (gpio_fn) {
296 case 0:
297 gpio_ctl->mode = STM32_GPIO_MODE_IN;
298 break;
299 case 1 ... 16:
300 gpio_ctl->mode = STM32_GPIO_MODE_AF;
301 gpio_ctl->af = gpio_fn - 1;
302 break;
303 case 17:
304 gpio_ctl->mode = STM32_GPIO_MODE_AN;
305 break;
306 default:
307 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
308 break;
309 }
310
311 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
312
313 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
314 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
315 else
316 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
317
318 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
319 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
320 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
321 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
322 else
323 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
324
325 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
326 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
327 gpio_ctl->pupd);
328
329 return 0;
330}
331
332static int stm32_pinctrl_config(int offset)
333{
334 u32 pin_mux[MAX_PINS_ONE_IP];
335 int rv, len;
336
337
338
339
340
341 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
342 struct stm32_gpio_dsc gpio_dsc;
343 struct stm32_gpio_ctl gpio_ctl;
344 int i;
345
346 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
347 "pinmux", pin_mux,
348 ARRAY_SIZE(pin_mux));
349 debug("%s: no of pinmux entries= %d\n", __func__, len);
350 if (len < 0)
351 return -EINVAL;
352 for (i = 0; i < len; i++) {
353 struct gpio_desc desc;
354
355 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
356 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
357 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
358 rv = uclass_get_device_by_seq(UCLASS_GPIO,
359 gpio_dsc.port,
360 &desc.dev);
361 if (rv)
362 return rv;
363 desc.offset = gpio_dsc.pin;
364 rv = stm32_gpio_config(&desc, &gpio_ctl);
365 debug("%s: rv = %d\n\n", __func__, rv);
366 if (rv)
367 return rv;
368 }
369 }
370
371 return 0;
372}
373
374static int stm32_pinctrl_bind(struct udevice *dev)
375{
376 ofnode node;
377 const char *name;
378 int ret;
379
380 dev_for_each_subnode(node, dev) {
381 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
382
383 ofnode_get_property(node, "gpio-controller", &ret);
384 if (ret < 0)
385 continue;
386
387 name = ofnode_get_name(node);
388 if (!name)
389 return -EINVAL;
390
391
392 ret = device_bind_driver_to_node(dev, "gpio_stm32",
393 name, node, NULL);
394 if (ret)
395 return ret;
396
397 debug("%s: bind %s\n", __func__, name);
398 }
399
400 return 0;
401}
402
403#if CONFIG_IS_ENABLED(PINCTRL_FULL)
404static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
405{
406 return stm32_pinctrl_config(dev_of_offset(config));
407}
408#else
409static int stm32_pinctrl_set_state_simple(struct udevice *dev,
410 struct udevice *periph)
411{
412 const void *fdt = gd->fdt_blob;
413 const fdt32_t *list;
414 uint32_t phandle;
415 int config_node;
416 int size, i, ret;
417
418 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
419 if (!list)
420 return -EINVAL;
421
422 debug("%s: periph->name = %s\n", __func__, periph->name);
423
424 size /= sizeof(*list);
425 for (i = 0; i < size; i++) {
426 phandle = fdt32_to_cpu(*list++);
427
428 config_node = fdt_node_offset_by_phandle(fdt, phandle);
429 if (config_node < 0) {
430 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
431 return -EINVAL;
432 }
433
434 ret = stm32_pinctrl_config(config_node);
435 if (ret)
436 return ret;
437 }
438
439 return 0;
440}
441#endif
442
443static struct pinctrl_ops stm32_pinctrl_ops = {
444#if CONFIG_IS_ENABLED(PINCTRL_FULL)
445 .set_state = stm32_pinctrl_set_state,
446#else
447 .set_state_simple = stm32_pinctrl_set_state_simple,
448#endif
449#ifndef CONFIG_SPL_BUILD
450 .get_pin_name = stm32_pinctrl_get_pin_name,
451 .get_pins_count = stm32_pinctrl_get_pins_count,
452 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
453#endif
454};
455
456static const struct udevice_id stm32_pinctrl_ids[] = {
457 { .compatible = "st,stm32f429-pinctrl" },
458 { .compatible = "st,stm32f469-pinctrl" },
459 { .compatible = "st,stm32f746-pinctrl" },
460 { .compatible = "st,stm32f769-pinctrl" },
461 { .compatible = "st,stm32h743-pinctrl" },
462 { .compatible = "st,stm32mp157-pinctrl" },
463 { .compatible = "st,stm32mp157-z-pinctrl" },
464 { }
465};
466
467U_BOOT_DRIVER(pinctrl_stm32) = {
468 .name = "pinctrl_stm32",
469 .id = UCLASS_PINCTRL,
470 .of_match = stm32_pinctrl_ids,
471 .ops = &stm32_pinctrl_ops,
472 .bind = stm32_pinctrl_bind,
473 .probe = stm32_pinctrl_probe,
474 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
475};
476
