LXR uboot/drivers/timer/stm32

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5 */
   6
   7#include <common.h>
   8#include <clk.h>
   9#include <dm.h>
  10#include <fdtdec.h>
  11#include <timer.h>
  12#include <dm/device_compat.h>
  13#include <linux/bitops.h>
  14
  15#include <asm/io.h>
  16
  17/* Timer control1 register  */
  18#define CR1_CEN                 BIT(0)
  19#define CR1_ARPE                BIT(7)
  20
  21/* Event Generation Register register  */
  22#define EGR_UG                  BIT(0)
  23
  24/* Auto reload register for free running config */
  25#define GPT_FREE_RUNNING        0xFFFFFFFF
  26
  27struct stm32_timer_regs {
  28        u32 cr1;
  29        u32 cr2;
  30        u32 smcr;
  31        u32 dier;
  32        u32 sr;
  33        u32 egr;
  34        u32 ccmr1;
  35        u32 ccmr2;
  36        u32 ccer;
  37        u32 cnt;
  38        u32 psc;
  39        u32 arr;
  40        u32 reserved;
  41        u32 ccr1;
  42        u32 ccr2;
  43        u32 ccr3;
  44        u32 ccr4;
  45        u32 reserved1;
  46        u32 dcr;
  47        u32 dmar;
  48        u32 tim2_5_or;
  49};
  50
  51struct stm32_timer_priv {
  52        struct stm32_timer_regs *base;
  53};
  54
  55static int stm32_timer_get_count(struct udevice *dev, u64 *count)
  56{
  57        struct stm32_timer_priv *priv = dev_get_priv(dev);
  58        struct stm32_timer_regs *regs = priv->base;
  59
  60        *count = readl(&regs->cnt);
  61
  62        return 0;
  63}
  64
  65static int stm32_timer_probe(struct udevice *dev)
  66{
  67        struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  68        struct stm32_timer_priv *priv = dev_get_priv(dev);
  69        struct stm32_timer_regs *regs;
  70        struct clk clk;
  71        fdt_addr_t addr;
  72        int ret;
  73        u32 rate, psc;
  74
  75        addr = dev_read_addr(dev);
  76        if (addr == FDT_ADDR_T_NONE)
  77                return -EINVAL;
  78
  79        priv->base = (struct stm32_timer_regs *)addr;
  80
  81        ret = clk_get_by_index(dev, 0, &clk);
  82        if (ret < 0)
  83                return ret;
  84
  85        ret = clk_enable(&clk);
  86        if (ret) {
  87                dev_err(dev, "failed to enable clock\n");
  88                return ret;
  89        }
  90
  91        regs = priv->base;
  92
  93        /* Stop the timer */
  94        clrbits_le32(&regs->cr1, CR1_CEN);
  95
  96        /* get timer clock */
  97        rate = clk_get_rate(&clk);
  98
  99        /* we set timer prescaler to obtain a 1MHz timer counter frequency */
 100        psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
 101        writel(psc, &regs->psc);
 102
 103        /* Set timer frequency to 1MHz */
 104        uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
 105
 106        /* Configure timer for auto-reload */
 107        setbits_le32(&regs->cr1, CR1_ARPE);
 108
 109        /* load value for auto reload */
 110        writel(GPT_FREE_RUNNING, &regs->arr);
 111
 112        /* start timer */
 113        setbits_le32(&regs->cr1, CR1_CEN);
 114
 115        /* Update generation */
 116        setbits_le32(&regs->egr, EGR_UG);
 117
 118        return 0;
 119}
 120
 121static const struct timer_ops stm32_timer_ops = {
 122        .get_count = stm32_timer_get_count,
 123};
 124
 125static const struct udevice_id stm32_timer_ids[] = {
 126        { .compatible = "st,stm32-timer" },
 127        {}
 128};
 129
 130U_BOOT_DRIVER(stm32_timer) = {
 131        .name = "stm32_timer",
 132        .id = UCLASS_TIMER,
 133        .of_match = stm32_timer_ids,
 134        .priv_auto_alloc_size = sizeof(struct stm32_timer_priv),
 135        .probe = stm32_timer_probe,
 136        .ops = &stm32_timer_ops,
 137};
 138
 139