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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <linux/stringify.h>
14
15#ifdef CONFIG_SPIFLASH
16#define CONFIG_RAMBOOT_SPIFLASH
17#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
18#endif
19
20#ifdef CONFIG_MTD_RAW_NAND
21#ifdef CONFIG_TPL_BUILD
22#define CONFIG_SPL_FLUSH_IMAGE
23#define CONFIG_SPL_NAND_INIT
24#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
25#define CONFIG_SPL_COMMON_INIT_DDR
26#define CONFIG_SPL_MAX_SIZE (128 << 10)
27#define CONFIG_TPL_TEXT_BASE 0xf8f81000
28#define CONFIG_SYS_MPC85XX_NO_RESETVEC
29#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
30#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
31#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
32#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
33#elif defined(CONFIG_SPL_BUILD)
34#define CONFIG_SPL_INIT_MINIMAL
35#define CONFIG_SPL_NAND_MINIMAL
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_MAX_SIZE 8192
38#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
39#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
40#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
41#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
42#endif
43#define CONFIG_SPL_PAD_TO 0x20000
44#define CONFIG_TPL_PAD_TO 0x20000
45#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46#endif
47
48#ifndef CONFIG_RESET_VECTOR_ADDRESS
49#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
50#endif
51
52#ifdef CONFIG_TPL_BUILD
53#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
54#elif defined(CONFIG_SPL_BUILD)
55#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
56#else
57#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
58#endif
59
60#ifdef CONFIG_SPL_BUILD
61#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
62#endif
63
64
65#define CONFIG_SYS_HAS_SERDES
66
67#ifdef CONFIG_PCI
68#define CONFIG_PCIE1
69#define CONFIG_FSL_PCI_INIT
70#define CONFIG_PCI_INDIRECT_BRIDGE
71#define CONFIG_SYS_PCI_64BIT
72
73
74
75
76
77
78#define CONFIG_SYS_PCIE1_NAME "Slot 1"
79#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
80#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
81#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
82#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
83#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
84#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
85#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
86#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
87
88#define CONFIG_PCI_SCAN_SHOW
89#endif
90
91#define CONFIG_ENV_OVERWRITE
92
93#define CONFIG_DDR_CLK_FREQ 100000000
94#define CONFIG_SYS_CLK_FREQ 66666666
95
96#define CONFIG_HWCONFIG
97
98
99
100
101#define CONFIG_L2_CACHE
102#define CONFIG_BTB
103
104
105#define CONFIG_ENABLE_36BIT_PHYS
106
107#define CONFIG_ADDR_MAP 1
108#define CONFIG_SYS_NUM_ADDR_MAP 16
109
110
111#define CONFIG_DDR_SPD
112#define CONFIG_SYS_SPD_BUS_NUM 0
113#define SPD_EEPROM_ADDRESS 0x50
114#define CONFIG_SYS_DDR_RAW_TIMING
115
116
117#define CONFIG_DDR_ECC
118#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
119#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120
121#define CONFIG_SYS_SDRAM_SIZE 512
122#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
124
125#define CONFIG_DIMM_SLOTS_PER_CTLR 1
126#define CONFIG_CHIP_SELECTS_PER_CTRL 1
127
128#define CONFIG_SYS_CCSRBAR 0xffe00000
129#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130
131
132#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
133#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
134 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
135#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
136
137
138
139
140
141#define CONFIG_SYS_FLASH_BASE 0xec000000
142#define CONFIG_SYS_MAX_FLASH_SECT 512
143
144#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
145
146#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
147#define CONFIG_SYS_MAX_FLASH_BANKS 1
148
149#define CONFIG_SYS_FLASH_QUIET_TEST
150#define CONFIG_FLASH_SHOW_PROGRESS 45
151#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500
153
154
155#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
156 CSPR_PORT_SIZE_16 | \
157 CSPR_MSEL_NOR | \
158 CSPR_V)
159#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
160#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
161
162#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
163 FTIM0_NOR_TEADC(0x5) | \
164 FTIM0_NOR_TEAHC(0x5))
165#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
166 FTIM1_NOR_TRAD_NOR(0x1A) |\
167 FTIM1_NOR_TSEQRAD_NOR(0x13))
168#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
169 FTIM2_NOR_TCH(0x4) | \
170 FTIM2_NOR_TWPH(0x0E) | \
171 FTIM2_NOR_TWP(0x1c))
172#define CONFIG_SYS_NOR_FTIM3 0x0
173
174
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176
177
178#define CONFIG_NAND_FSL_IFC
179#define CONFIG_SYS_NAND_BASE 0xff800000
180#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
181
182#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
183
184#define CONFIG_SYS_MAX_NAND_DEVICE 1
185#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
186
187
188#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
189 | CSPR_PORT_SIZE_8 \
190 | CSPR_MSEL_NAND \
191 | CSPR_V)
192#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
193#define CONFIG_SYS_NAND_OOBSIZE 0x00000280
194#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
195 | CSOR_NAND_ECC_DEC_EN \
196 | CSOR_NAND_ECC_MODE_4 \
197 | CSOR_NAND_RAL_3 \
198 | CSOR_NAND_PGS_8K \
199 | CSOR_NAND_SPRZ_CSOR_EXT \
200 | CSOR_NAND_PB(128))
201#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
202 FTIM0_NAND_TWP(0x0c) | \
203 FTIM0_NAND_TWCHT(0x08) | \
204 FTIM0_NAND_TWH(0x06))
205#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
206 FTIM1_NAND_TWBE(0x1d) | \
207 FTIM1_NAND_TRR(0x08) | \
208 FTIM1_NAND_TRP(0x0c))
209#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
210 FTIM2_NAND_TREH(0x0a) | \
211 FTIM2_NAND_TWHRE(0x18))
212#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
213
214#define CONFIG_SYS_NAND_DDR_LAW 11
215
216
217#ifdef CONFIG_MTD_RAW_NAND
218#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
219#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
220#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
221#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
222#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
223#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
224#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
225#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
226#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
227#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
228#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
229#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
230#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
231#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
232#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
233#else
234#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
235#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
236#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
237#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
238#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
239#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
240#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
241#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
242#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
243#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
244#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
245#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
246#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
247#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
248#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
249#endif
250
251
252#define CONFIG_SYS_CPLD_BASE 0xffdf0000
253#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
254 | CONFIG_SYS_CPLD_BASE)
255
256#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
257 | CSPR_PORT_SIZE_8 \
258 | CSPR_MSEL_GPCM \
259 | CSPR_V)
260#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
261#define CONFIG_SYS_CSOR2 0x0
262
263#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
264 FTIM0_GPCM_TEADC(0x0e) | \
265 FTIM0_GPCM_TEAHC(0x0e))
266#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
267 FTIM1_GPCM_TRAD(0x1f))
268#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
269 FTIM2_GPCM_TCH(0x8) | \
270 FTIM2_GPCM_TWP(0x1f))
271#define CONFIG_SYS_CS2_FTIM3 0x0
272
273#if defined(CONFIG_RAMBOOT_SPIFLASH)
274#define CONFIG_SYS_RAMBOOT
275#endif
276
277#define CONFIG_SYS_INIT_RAM_LOCK
278#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
279#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
280
281#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
282 - GENERATED_GBL_DATA_SIZE)
283#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
284
285#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
286#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
287
288
289
290
291#if defined(CONFIG_SPL_BUILD)
292#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
293#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
294#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
295#define CONFIG_SYS_L2_SIZE (256 << 10)
296#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
297#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
298#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
299#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
300#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
301#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
302#elif defined(CONFIG_MTD_RAW_NAND)
303#ifdef CONFIG_TPL_BUILD
304#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
305#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
306#define CONFIG_SYS_L2_SIZE (256 << 10)
307#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
308#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
309#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
310#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
311#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
312#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
313#else
314#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
315#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
316#define CONFIG_SYS_L2_SIZE (256 << 10)
317#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
318#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
319#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
320#endif
321#endif
322#endif
323
324
325#define CONFIG_SYS_NS16550_SERIAL
326#define CONFIG_SYS_NS16550_REG_SIZE 1
327#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
328
329#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
330#define CONFIG_NS16550_MIN_FUNCTIONS
331#endif
332
333#define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
335
336#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
337#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
338
339#define CONFIG_SYS_I2C
340#define CONFIG_SYS_I2C_FSL
341#define CONFIG_SYS_FSL_I2C_SPEED 400000
342#define CONFIG_SYS_FSL_I2C2_SPEED 400000
343#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
344#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
345#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
346#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
347
348
349
350#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
351#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
352#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
353
354
355
356#ifdef CONFIG_TSEC_ENET
357#define CONFIG_MII_DEFAULT_TSEC 1
358#define CONFIG_TSEC1 1
359#define CONFIG_TSEC1_NAME "eTSEC1"
360#define CONFIG_TSEC2 1
361#define CONFIG_TSEC2_NAME "eTSEC2"
362
363
364#define TSEC1_PHY_ADDR 0
365#define TSEC2_PHY_ADDR 2
366
367#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
369
370#define CONFIG_ETHPRIME "eTSEC1"
371#endif
372
373
374
375
376#if defined(CONFIG_SYS_RAMBOOT)
377#elif defined(CONFIG_MTD_RAW_NAND)
378#ifdef CONFIG_TPL_BUILD
379#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
380#else
381#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
382#endif
383#endif
384
385#define CONFIG_LOADS_ECHO
386#define CONFIG_SYS_LOADS_BAUD_CHANGE
387
388
389
390
391#define CONFIG_SYS_LOAD_ADDR 0x2000000
392
393
394
395
396
397
398#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
399#define CONFIG_SYS_BOOTM_LEN (64 << 20)
400
401
402
403
404
405#ifdef CONFIG_TSEC_ENET
406#define CONFIG_HAS_ETH0
407#define CONFIG_HAS_ETH1
408#endif
409
410#define CONFIG_ROOTPATH "/opt/nfsroot"
411#define CONFIG_BOOTFILE "uImage"
412#define CONFIG_UBOOTPATH u-boot.bin
413
414
415#define CONFIG_LOADADDR 1000000
416
417#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
418
419#define CONFIG_EXTRA_ENV_SETTINGS \
420 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
421 "netdev=eth0\0" \
422 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
423 "loadaddr=1000000\0" \
424 "consoledev=ttyS0\0" \
425 "ramdiskaddr=2000000\0" \
426 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
427 "fdtaddr=1e00000\0" \
428 "fdtfile=name/of/device-tree.dtb\0" \
429 "othbootargs=ramdisk_size=600000\0" \
430
431#define CONFIG_RAMBOOTCOMMAND \
432 "setenv bootargs root=/dev/ram rw " \
433 "console=$consoledev,$baudrate $othbootargs; " \
434 "tftp $ramdiskaddr $ramdiskfile;" \
435 "tftp $loadaddr $bootfile;" \
436 "tftp $fdtaddr $fdtfile;" \
437 "bootm $loadaddr $ramdiskaddr $fdtaddr"
438
439#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
440
441#include <asm/fsl_secure_boot.h>
442
443#endif
444