/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300             1 /* E300 family */

/*
 * IP blocks clock configuration
 */
#define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
#define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
#define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH                0x00000000
#define CONFIG_SYS_SICRL                0x00000000

/*
 * Output Buffer Impedance
 */
#define CONFIG_SYS_OBIR         0x31100000

#define CONFIG_HWCONFIG

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
                                        | DDRCDR_ODT \
                                        | DDRCDR_Q_DRN)
                                        /* 0x80080001 */ /* ODT 150ohm on SoC */

#undef CONFIG_DDR_ECC           /* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */

#define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */

#if defined(CONFIG_SPD_EEPROM)
#define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
#else
/*
 * Manually set up DDR parameters
 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 */
#define CONFIG_SYS_DDR_SIZE             512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
                        | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
                        | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
                        | CSCONFIG_ROW_BIT_14 \
                        | CSCONFIG_COL_BIT_10)
                        /* 0x80010202 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
                                | (0 << TIMING_CFG0_WRT_SHIFT) \
                                | (0 << TIMING_CFG0_RRT_SHIFT) \
                                | (0 << TIMING_CFG0_WWT_SHIFT) \
                                | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
                                | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
                                | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
                                | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
                                /* 0x00620802 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
                                | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
                                | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
                                | (5 << TIMING_CFG1_CASLAT_SHIFT) \
                                | (13 << TIMING_CFG1_REFREC_SHIFT) \
                                | (3 << TIMING_CFG1_WRREC_SHIFT) \
                                | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
                                | (2 << TIMING_CFG1_WRTORD_SHIFT))
                                /* 0x3935d322 */
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
                                | (6 << TIMING_CFG2_CPO_SHIFT) \
                                | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
                                | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
                                | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
                                | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
                                | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
                                /* 0x131088c8 */
#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
                                | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
                                /* 0x03E00100 */
#define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
                                | (0x1432 << SDRAM_MODE_SD_SHIFT))
                                /* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2    0x00000000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK        1
#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET      \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */


#define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */

/*
 * BCSR on the Local Bus
 */
#define CONFIG_SYS_BCSR         0xF8000000
                                        /* Access window base at BCSR base */

/*
 * NAND Flash on the Local Bus
 */
#define CONFIG_SYS_MAX_NAND_DEVICE      1
#define CONFIG_NAND_FSL_ELBC    1

#define CONFIG_SYS_NAND_BASE    0xE0600000


/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED        400000
#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI_MEM_BASE         0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE          0x00000000
#define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000

#define CONFIG_SYS_PCIE1_BASE           0xA0000000
#define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
#define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
#define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
#define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
#define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000

#define CONFIG_SYS_PCIE2_BASE           0xC0000000
#define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
#define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
#define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
#define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
#define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
#define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#ifndef __ASSEMBLY__
extern int board_pci_host_broken(void);
#endif
#define CONFIG_PCIE
#define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */

#define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
#endif /* CONFIG_PCI */

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1            1
#define CONFIG_TSEC1_NAME       "eTSEC0"
#define CONFIG_TSEC2            1
#define CONFIG_TSEC2_NAME       "eTSEC1"
#define TSEC1_PHY_ADDR          2
#define TSEC2_PHY_ADDR          3
#define TSEC1_PHY_ADDR_SGMII    8
#define TSEC2_PHY_ADDR_SGMII    4
#define TSEC1_PHYIDX            0
#define TSEC2_PHYIDX            0
#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME         "eTSEC1"

/* SERDES */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1      0xe3000
#define CONFIG_FSL_SERDES2      0xe3100

/*
 * SATA
 */
#define CONFIG_SYS_SATA_MAX_DEVICE      2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
#define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG          /* watchdog disabled */

#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */

#define CONFIG_EXTRA_ENV_SETTINGS                                       \
        "netdev=eth0\0"                                                 \
        "consoledev=ttyS0\0"                                            \
        "ramdiskaddr=1000000\0"                                         \
        "ramdiskfile=ramfs.83xx\0"                                      \
        "fdtaddr=780000\0"                                              \
        "fdtfile=mpc8379_mds.dtb\0"                                     \
        ""

#define CONFIG_NFSBOOTCOMMAND                                           \
        "setenv bootargs root=/dev/nfs rw "                             \
                "nfsroot=$serverip:$rootpath "                          \
                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
                                                        "$netdev:off "  \
                "console=$consoledev,$baudrate $othbootargs;"           \
        "tftp $loadaddr $bootfile;"                                     \
        "tftp $fdtaddr $fdtfile;"                                       \
        "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND                                           \
        "setenv bootargs root=/dev/ram rw "                             \
                "console=$consoledev,$baudrate $othbootargs;"           \
        "tftp $ramdiskaddr $ramdiskfile;"                               \
        "tftp $loadaddr $bootfile;"                                     \
        "tftp $fdtaddr $fdtfile;"                                       \
        "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif  /* __CONFIG_H */