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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define CONFIG_SYS_SRIO
17#define CONFIG_SRIO1
18
19#define CONFIG_PCI1
20#define CONFIG_PCIE1
21#undef CONFIG_PCI2
22#define CONFIG_SYS_PCI_64BIT 1
23
24#define CONFIG_ENV_OVERWRITE
25#define CONFIG_INTERRUPTS
26
27#define CONFIG_FSL_VIA
28
29#ifndef __ASSEMBLY__
30#include <linux/stringify.h>
31extern unsigned long get_clock_freq(void);
32#endif
33#define CONFIG_SYS_CLK_FREQ get_clock_freq()
34
35
36
37
38#define CONFIG_L2_CACHE
39#define CONFIG_BTB
40
41
42
43
44#define CONFIG_ENABLE_36BIT_PHYS 1
45
46#ifdef CONFIG_PHYS_64BIT
47#define CONFIG_ADDR_MAP
48#define CONFIG_SYS_NUM_ADDR_MAP 16
49#endif
50
51#define CONFIG_SYS_CCSRBAR 0xe0000000
52#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
53
54
55#define CONFIG_SPD_EEPROM
56#define CONFIG_DDR_SPD
57
58#define CONFIG_DDR_ECC
59#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
60#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
61
62#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
63#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
64
65#define CONFIG_DIMM_SLOTS_PER_CTLR 1
66#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
67
68
69#define SPD_EEPROM_ADDRESS 0x51
70
71
72#ifndef CONFIG_SPD_EEPROM
73#error ("CONFIG_SPD_EEPROM is required")
74#endif
75
76#undef CONFIG_CLOCKS_IN_MHZ
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142#define CONFIG_SYS_FLASH_BASE 0xff000000
143#ifdef CONFIG_PHYS_64BIT
144#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
145#else
146#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
147#endif
148
149#define CONFIG_SYS_BR0_PRELIM \
150 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
151#define CONFIG_SYS_BR1_PRELIM \
152 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
153
154#define CONFIG_SYS_OR0_PRELIM 0xff806e65
155#define CONFIG_SYS_OR1_PRELIM 0xff806e65
156
157#define CONFIG_SYS_FLASH_BANKS_LIST \
158 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
159#define CONFIG_SYS_MAX_FLASH_BANKS 2
160#define CONFIG_SYS_MAX_FLASH_SECT 128
161#undef CONFIG_SYS_FLASH_CHECKSUM
162#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
163#define CONFIG_SYS_FLASH_WRITE_TOUT 500
164
165#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
166
167#define CONFIG_SYS_FLASH_EMPTY_INFO
168
169#define CONFIG_HWCONFIG
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173
174#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
175#ifdef CONFIG_PHYS_64BIT
176#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
177#else
178#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
179#endif
180#define CONFIG_SYS_LBC_SDRAM_SIZE 64
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200#define CONFIG_SYS_BR2_PRELIM \
201 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
202 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
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218#define CONFIG_SYS_OR2_PRELIM 0xfc006901
219
220#define CONFIG_SYS_LBC_LCRR 0x00030004
221#define CONFIG_SYS_LBC_LBCR 0x00000000
222#define CONFIG_SYS_LBC_LSRT 0x20000000
223#define CONFIG_SYS_LBC_MRTPR 0x00000000
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230
231#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
232 | LSDMR_PRETOACT7 \
233 | LSDMR_ACTTORW7 \
234 | LSDMR_BL8 \
235 | LSDMR_WRC4 \
236 | LSDMR_CL3 \
237 | LSDMR_RFEN \
238 )
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270#define CONFIG_FSL_CADMUS
271
272#define CADMUS_BASE_ADDR 0xf8000000
273#ifdef CONFIG_PHYS_64BIT
274#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
275#else
276#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
277#endif
278#define CONFIG_SYS_BR3_PRELIM \
279 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
280#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
281
282#define CONFIG_SYS_INIT_RAM_LOCK 1
283#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
284#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
285
286#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
287#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
288
289#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
290#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
291
292
293#define CONFIG_SYS_NS16550_SERIAL
294#define CONFIG_SYS_NS16550_REG_SIZE 1
295#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
296
297#define CONFIG_SYS_BAUDRATE_TABLE \
298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
299
300#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
301#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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305
306#ifndef CONFIG_DM_I2C
307#define CONFIG_SYS_I2C
308#define CONFIG_SYS_FSL_I2C_SPEED 400000
309#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
310#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
311#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
312#else
313#define CONFIG_SYS_SPD_BUS_NUM 0
314#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
315#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
316#endif
317#define CONFIG_SYS_I2C_FSL
318
319
320#define CONFIG_ID_EEPROM
321#define CONFIG_SYS_I2C_EEPROM_CCID
322#define CONFIG_SYS_ID_EEPROM
323#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
324#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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329
330#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
331#ifdef CONFIG_PHYS_64BIT
332#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
333#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
334#else
335#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
336#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
337#endif
338#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
339#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
340#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
341#ifdef CONFIG_PHYS_64BIT
342#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
343#else
344#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
345#endif
346#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
347
348#ifdef CONFIG_PCIE1
349#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
350#ifdef CONFIG_PHYS_64BIT
351#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
352#else
353#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
354#endif
355#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
356#ifdef CONFIG_PHYS_64BIT
357#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
358#else
359#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
360#endif
361#endif
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365
366#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
367#ifdef CONFIG_PHYS_64BIT
368#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
369#else
370#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
371#endif
372#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
373
374#ifdef CONFIG_LEGACY
375#define BRIDGE_ID 17
376#define VIA_ID 2
377#else
378#define BRIDGE_ID 28
379#define VIA_ID 4
380#endif
381
382#if defined(CONFIG_PCI)
383#undef CONFIG_EEPRO100
384#undef CONFIG_TULIP
385
386#if !defined(CONFIG_DM_PCI)
387#define CONFIG_FSL_PCI_INIT 1
388#define CONFIG_PCI_INDIRECT_BRIDGE 1
389#define CONFIG_SYS_PCIE1_NAME "Slot"
390#ifdef CONFIG_PHYS_64BIT
391#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
392#else
393#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
394#endif
395#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
396#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
397#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
398#endif
399
400#define CONFIG_PCI_SCAN_SHOW
401
402#endif
403
404#if defined(CONFIG_TSEC_ENET)
405
406#define CONFIG_TSEC1 1
407#define CONFIG_TSEC1_NAME "eTSEC0"
408#define CONFIG_TSEC2 1
409#define CONFIG_TSEC2_NAME "eTSEC1"
410#define CONFIG_TSEC3 1
411#define CONFIG_TSEC3_NAME "eTSEC2"
412#define CONFIG_TSEC4
413#define CONFIG_TSEC4_NAME "eTSEC3"
414#undef CONFIG_MPC85XX_FEC
415
416#define TSEC1_PHY_ADDR 0
417#define TSEC2_PHY_ADDR 1
418#define TSEC3_PHY_ADDR 2
419#define TSEC4_PHY_ADDR 3
420
421#define TSEC1_PHYIDX 0
422#define TSEC2_PHYIDX 0
423#define TSEC3_PHYIDX 0
424#define TSEC4_PHYIDX 0
425#define TSEC1_FLAGS TSEC_GIGABIT
426#define TSEC2_FLAGS TSEC_GIGABIT
427#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
428#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
429
430
431#define CONFIG_ETHPRIME "eTSEC0"
432#endif
433
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437
438#define CONFIG_LOADS_ECHO 1
439#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
440
441
442
443
444#define CONFIG_BOOTP_BOOTFILESIZE
445
446#undef CONFIG_WATCHDOG
447
448
449
450
451#define CONFIG_SYS_LOAD_ADDR 0x2000000
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453
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456
457
458#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
459#define CONFIG_SYS_BOOTM_LEN (64 << 20)
460
461#if defined(CONFIG_CMD_KGDB)
462#define CONFIG_KGDB_BAUDRATE 230400
463#endif
464
465
466
467
468#if defined(CONFIG_TSEC_ENET)
469#define CONFIG_HAS_ETH0
470#define CONFIG_HAS_ETH1
471#define CONFIG_HAS_ETH2
472#define CONFIG_HAS_ETH3
473#endif
474
475#define CONFIG_IPADDR 192.168.1.253
476
477#define CONFIG_HOSTNAME "unknown"
478#define CONFIG_ROOTPATH "/nfsroot"
479#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
480#define CONFIG_UBOOTPATH 8548cds/u-boot.bin
481
482#define CONFIG_SERVERIP 192.168.1.1
483#define CONFIG_GATEWAYIP 192.168.1.1
484#define CONFIG_NETMASK 255.255.255.0
485
486#define CONFIG_LOADADDR 1000000
487
488#define CONFIG_EXTRA_ENV_SETTINGS \
489 "hwconfig=fsl_ddr:ecc=off\0" \
490 "netdev=eth0\0" \
491 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
492 "tftpflash=tftpboot $loadaddr $uboot; " \
493 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
494 " +$filesize; " \
495 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
496 " +$filesize; " \
497 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
498 " $filesize; " \
499 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
500 " +$filesize; " \
501 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
502 " $filesize\0" \
503 "consoledev=ttyS1\0" \
504 "ramdiskaddr=2000000\0" \
505 "ramdiskfile=ramdisk.uboot\0" \
506 "fdtaddr=1e00000\0" \
507 "fdtfile=mpc8548cds.dtb\0"
508
509#define CONFIG_NFSBOOTCOMMAND \
510 "setenv bootargs root=/dev/nfs rw " \
511 "nfsroot=$serverip:$rootpath " \
512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
513 "console=$consoledev,$baudrate $othbootargs;" \
514 "tftp $loadaddr $bootfile;" \
515 "tftp $fdtaddr $fdtfile;" \
516 "bootm $loadaddr - $fdtaddr"
517
518#define CONFIG_RAMBOOTCOMMAND \
519 "setenv bootargs root=/dev/ram rw " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "tftp $ramdiskaddr $ramdiskfile;" \
522 "tftp $loadaddr $bootfile;" \
523 "tftp $fdtaddr $fdtfile;" \
524 "bootm $loadaddr $ramdiskaddr $fdtaddr"
525
526#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
527
528#endif
529