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5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#include <linux/stringify.h>
11
12
13
14
15#include <asm/config_mpc85xx.h>
16
17#ifdef CONFIG_RAMBOOT_PBL
18
19#ifndef CONFIG_NXP_ESBC
20#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
21#else
22#define CONFIG_SYS_FSL_PBL_PBI \
23 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
24#endif
25
26#define CONFIG_SPL_FLUSH_IMAGE
27#define CONFIG_SPL_PAD_TO 0x40000
28#define CONFIG_SPL_MAX_SIZE 0x28000
29#ifdef CONFIG_SPL_BUILD
30#define CONFIG_SPL_SKIP_RELOCATE
31#define CONFIG_SPL_COMMON_INIT_DDR
32#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
33#undef CONFIG_DM_I2C
34#endif
35#define RESET_VECTOR_OFFSET 0x27FFC
36#define BOOT_PAGE_OFFSET 0x27000
37
38#ifdef CONFIG_MTD_RAW_NAND
39#ifdef CONFIG_NXP_ESBC
40#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
41
42
43
44
45#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
46 CONFIG_U_BOOT_HDR_SIZE)
47#else
48#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#endif
50#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
52#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
53#ifdef CONFIG_TARGET_T1040RDB
54#define CONFIG_SYS_FSL_PBL_RCW \
55$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
56#endif
57#ifdef CONFIG_TARGET_T1042RDB_PI
58#define CONFIG_SYS_FSL_PBL_RCW \
59$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
60#endif
61#ifdef CONFIG_TARGET_T1042RDB
62#define CONFIG_SYS_FSL_PBL_RCW \
63$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
64#endif
65#ifdef CONFIG_TARGET_T1040D4RDB
66#define CONFIG_SYS_FSL_PBL_RCW \
67$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
68#endif
69#ifdef CONFIG_TARGET_T1042D4RDB
70#define CONFIG_SYS_FSL_PBL_RCW \
71$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
72#endif
73#endif
74
75#ifdef CONFIG_SPIFLASH
76#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
77#define CONFIG_SPL_SPI_FLASH_MINIMAL
78#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
79#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
80#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
81#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
82#ifndef CONFIG_SPL_BUILD
83#define CONFIG_SYS_MPC85XX_NO_RESETVEC
84#endif
85#ifdef CONFIG_TARGET_T1040RDB
86#define CONFIG_SYS_FSL_PBL_RCW \
87$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
88#endif
89#ifdef CONFIG_TARGET_T1042RDB_PI
90#define CONFIG_SYS_FSL_PBL_RCW \
91$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
92#endif
93#ifdef CONFIG_TARGET_T1042RDB
94#define CONFIG_SYS_FSL_PBL_RCW \
95$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
96#endif
97#ifdef CONFIG_TARGET_T1040D4RDB
98#define CONFIG_SYS_FSL_PBL_RCW \
99$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
100#endif
101#ifdef CONFIG_TARGET_T1042D4RDB
102#define CONFIG_SYS_FSL_PBL_RCW \
103$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
104#endif
105#endif
106
107#ifdef CONFIG_SDCARD
108#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
109#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
110#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
111#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
112#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
113#ifndef CONFIG_SPL_BUILD
114#define CONFIG_SYS_MPC85XX_NO_RESETVEC
115#endif
116#ifdef CONFIG_TARGET_T1040RDB
117#define CONFIG_SYS_FSL_PBL_RCW \
118$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
119#endif
120#ifdef CONFIG_TARGET_T1042RDB_PI
121#define CONFIG_SYS_FSL_PBL_RCW \
122$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
123#endif
124#ifdef CONFIG_TARGET_T1042RDB
125#define CONFIG_SYS_FSL_PBL_RCW \
126$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
127#endif
128#ifdef CONFIG_TARGET_T1040D4RDB
129#define CONFIG_SYS_FSL_PBL_RCW \
130$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
131#endif
132#ifdef CONFIG_TARGET_T1042D4RDB
133#define CONFIG_SYS_FSL_PBL_RCW \
134$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
135#endif
136#endif
137
138#endif
139
140
141#define CONFIG_SYS_BOOK3E_HV
142
143
144#define CONFIG_DEEP_SLEEP
145
146#ifndef CONFIG_RESET_VECTOR_ADDRESS
147#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
148#endif
149
150#define CONFIG_SYS_FSL_CPC
151#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
152#define CONFIG_PCIE1
153#define CONFIG_PCIE2
154#define CONFIG_PCIE3
155#define CONFIG_PCIE4
156
157#define CONFIG_SYS_PCI_64BIT
158
159#define CONFIG_ENV_OVERWRITE
160
161#if defined(CONFIG_SPIFLASH)
162#elif defined(CONFIG_SDCARD)
163#define CONFIG_SYS_MMC_ENV_DEV 0
164#elif defined(CONFIG_MTD_RAW_NAND)
165#ifdef CONFIG_NXP_ESBC
166#define CONFIG_RAMBOOT_NAND
167#define CONFIG_BOOTSCRIPT_COPY_RAM
168#endif
169#endif
170
171#define CONFIG_SYS_CLK_FREQ 100000000
172#define CONFIG_DDR_CLK_FREQ 66666666
173
174
175
176
177#define CONFIG_SYS_CACHE_STASHING
178#define CONFIG_BACKSIDE_L2_CACHE
179#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
180#define CONFIG_BTB
181#define CONFIG_DDR_ECC
182#ifdef CONFIG_DDR_ECC
183#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
184#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
185#endif
186
187#define CONFIG_ENABLE_36BIT_PHYS
188
189#define CONFIG_ADDR_MAP
190#define CONFIG_SYS_NUM_ADDR_MAP 64
191
192
193
194
195#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
196
197
198
199
200
201#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
202#define CONFIG_SYS_L3_SIZE 256 << 10
203#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
204#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
205#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
206#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
207#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
208
209#define CONFIG_SYS_DCSRBAR 0xf0000000
210#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
211
212
213
214
215#define CONFIG_VERY_BIG_RAM
216#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
217#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
218
219#define CONFIG_DIMM_SLOTS_PER_CTLR 1
220#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
221
222#define CONFIG_DDR_SPD
223
224#define CONFIG_SYS_SPD_BUS_NUM 0
225#define SPD_EEPROM_ADDRESS 0x51
226
227#define CONFIG_SYS_SDRAM_SIZE 4096
228
229
230
231
232#define CONFIG_SYS_FLASH_BASE 0xe8000000
233#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
234
235#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
236#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
237 CSPR_PORT_SIZE_16 | \
238 CSPR_MSEL_NOR | \
239 CSPR_V)
240#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
241
242
243
244
245#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
246
247
248#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
249#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
250 FTIM0_NOR_TEADC(0x5) | \
251 FTIM0_NOR_TEAHC(0x5))
252#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
253 FTIM1_NOR_TRAD_NOR(0x1A) |\
254 FTIM1_NOR_TSEQRAD_NOR(0x13))
255#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
256 FTIM2_NOR_TCH(0x4) | \
257 FTIM2_NOR_TWPH(0x0E) | \
258 FTIM2_NOR_TWP(0x1c))
259#define CONFIG_SYS_NOR_FTIM3 0x0
260
261#define CONFIG_SYS_FLASH_QUIET_TEST
262#define CONFIG_FLASH_SHOW_PROGRESS 45
263
264#define CONFIG_SYS_MAX_FLASH_BANKS 2
265#define CONFIG_SYS_MAX_FLASH_SECT 1024
266#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
267#define CONFIG_SYS_FLASH_WRITE_TOUT 500
268
269#define CONFIG_SYS_FLASH_EMPTY_INFO
270#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
271
272
273#define CPLD_LBMAP_MASK 0x3F
274#define CPLD_BANK_SEL_MASK 0x07
275#define CPLD_BANK_OVERRIDE 0x40
276#define CPLD_LBMAP_ALTBANK 0x44
277#define CPLD_LBMAP_DFLTBANK 0x40
278#define CPLD_LBMAP_RESET 0xFF
279#define CPLD_LBMAP_SHIFT 0x03
280
281#if defined(CONFIG_TARGET_T1042RDB_PI)
282#define CPLD_DIU_SEL_DFP 0x80
283#elif defined(CONFIG_TARGET_T1042D4RDB)
284#define CPLD_DIU_SEL_DFP 0xc0
285#endif
286
287#if defined(CONFIG_TARGET_T1040D4RDB)
288#define CPLD_INT_MASK_ALL 0xFF
289#define CPLD_INT_MASK_THERM 0x80
290#define CPLD_INT_MASK_DVI_DFP 0x40
291#define CPLD_INT_MASK_QSGMII1 0x20
292#define CPLD_INT_MASK_QSGMII2 0x10
293#define CPLD_INT_MASK_SGMI1 0x08
294#define CPLD_INT_MASK_SGMI2 0x04
295#define CPLD_INT_MASK_TDMR1 0x02
296#define CPLD_INT_MASK_TDMR2 0x01
297#endif
298
299#define CONFIG_SYS_CPLD_BASE 0xffdf0000
300#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
301#define CONFIG_SYS_CSPR2_EXT (0xf)
302#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
303 | CSPR_PORT_SIZE_8 \
304 | CSPR_MSEL_GPCM \
305 | CSPR_V)
306#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
307#define CONFIG_SYS_CSOR2 0x0
308
309#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
310 FTIM0_GPCM_TEADC(0x0e) | \
311 FTIM0_GPCM_TEAHC(0x0e))
312#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
313 FTIM1_GPCM_TRAD(0x1f))
314#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
315 FTIM2_GPCM_TCH(0x8) | \
316 FTIM2_GPCM_TWP(0x1f))
317#define CONFIG_SYS_CS2_FTIM3 0x0
318
319
320#define CONFIG_NAND_FSL_IFC
321#define CONFIG_SYS_NAND_BASE 0xff800000
322#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
323
324#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
325#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
326 | CSPR_PORT_SIZE_8 \
327 | CSPR_MSEL_NAND \
328 | CSPR_V)
329#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
330
331#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
332 | CSOR_NAND_ECC_DEC_EN \
333 | CSOR_NAND_ECC_MODE_4 \
334 | CSOR_NAND_RAL_3 \
335 | CSOR_NAND_PGS_4K \
336 | CSOR_NAND_SPRZ_224 \
337 | CSOR_NAND_PB(64))
338
339#define CONFIG_SYS_NAND_ONFI_DETECTION
340
341
342#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
343 FTIM0_NAND_TWP(0x18) | \
344 FTIM0_NAND_TWCHT(0x07) | \
345 FTIM0_NAND_TWH(0x0a))
346#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
347 FTIM1_NAND_TWBE(0x39) | \
348 FTIM1_NAND_TRR(0x0e) | \
349 FTIM1_NAND_TRP(0x18))
350#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
351 FTIM2_NAND_TREH(0x0a) | \
352 FTIM2_NAND_TWHRE(0x1e))
353#define CONFIG_SYS_NAND_FTIM3 0x0
354
355#define CONFIG_SYS_NAND_DDR_LAW 11
356#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
357#define CONFIG_SYS_MAX_NAND_DEVICE 1
358
359#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
360
361#if defined(CONFIG_MTD_RAW_NAND)
362#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
363#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
364#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
365#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
366#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
367#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
368#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
369#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
370#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
371#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
372#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
373#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
374#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
375#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
376#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
377#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
378#else
379#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
380#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
381#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
382#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
383#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
384#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
385#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
386#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
387#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
388#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
389#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
390#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
391#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
392#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
393#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
394#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
395#endif
396
397#ifdef CONFIG_SPL_BUILD
398#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
399#else
400#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
401#endif
402
403#if defined(CONFIG_RAMBOOT_PBL)
404#define CONFIG_SYS_RAMBOOT
405#endif
406
407#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
408#if defined(CONFIG_MTD_RAW_NAND)
409#define CONFIG_A008044_WORKAROUND
410#endif
411#endif
412
413#define CONFIG_HWCONFIG
414
415
416#define CONFIG_L1_INIT_RAM
417#define CONFIG_SYS_INIT_RAM_LOCK
418#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
419#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
420#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
421
422#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
423 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
424 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
425#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
426
427#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
428 GENERATED_GBL_DATA_SIZE)
429#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
430
431#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
432#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
433
434
435
436
437
438#define CONFIG_SYS_NS16550_SERIAL
439#define CONFIG_SYS_NS16550_REG_SIZE 1
440#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
441
442#define CONFIG_SYS_BAUDRATE_TABLE \
443 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
444
445#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
446#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
447#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
448#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
449
450#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
451
452#define CONFIG_FSL_DIU_FB
453
454#ifdef CONFIG_FSL_DIU_FB
455#define CONFIG_FSL_DIU_CH7301
456#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
457#define CONFIG_VIDEO_LOGO
458#define CONFIG_VIDEO_BMP_LOGO
459#endif
460#endif
461
462
463#ifndef CONFIG_DM_I2C
464#define CONFIG_SYS_I2C
465#define CONFIG_SYS_FSL_I2C_SPEED 400000
466#define CONFIG_SYS_FSL_I2C2_SPEED 400000
467#define CONFIG_SYS_FSL_I2C3_SPEED 400000
468#define CONFIG_SYS_FSL_I2C4_SPEED 400000
469#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
470#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
471#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
472#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
473#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
474#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
475#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
476#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
477#else
478#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
479#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
480#endif
481
482#define CONFIG_SYS_I2C_FSL
483
484#define I2C_MUX_PCA_ADDR 0x70
485#define I2C_MUX_CH_DEFAULT 0x8
486
487#if defined(CONFIG_TARGET_T1042RDB_PI) || \
488 defined(CONFIG_TARGET_T1040D4RDB) || \
489 defined(CONFIG_TARGET_T1042D4RDB)
490
491#define CONFIG_SYS_I2C_LDI_ADDR 0x38
492#define CONFIG_SYS_I2C_DVI_ADDR 0x75
493#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
494
495
496
497
498#define RTC
499#define CONFIG_RTC_DS1337 1
500#define CONFIG_SYS_I2C_RTC_ADDR 0x68
501
502
503#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
504#endif
505
506
507
508
509
510
511
512
513
514
515#ifdef CONFIG_PCI
516
517#ifdef CONFIG_PCIE1
518#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
519#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
520#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
521#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
522#endif
523
524
525#ifdef CONFIG_PCIE2
526#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
527#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
528#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
529#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
530#endif
531
532
533#ifdef CONFIG_PCIE3
534#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
535#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
536#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
537#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
538#endif
539
540
541#ifdef CONFIG_PCIE4
542#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
543#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
544#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
545#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
546#endif
547
548#if !defined(CONFIG_DM_PCI)
549#define CONFIG_FSL_PCI_INIT
550#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
551#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
552#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
553#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
554#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
555#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
556#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
557#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
558#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
559#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
560#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
561#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
562#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
563#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
564#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
565#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
566#define CONFIG_PCI_INDIRECT_BRIDGE
567#endif
568#define CONFIG_PCI_SCAN_SHOW
569#endif
570
571
572#define CONFIG_FSL_SATA_V2
573#ifdef CONFIG_FSL_SATA_V2
574#define CONFIG_SYS_SATA_MAX_DEVICE 1
575#define CONFIG_SATA1
576#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
577#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
578
579#define CONFIG_LBA48
580#endif
581
582
583
584
585#define CONFIG_HAS_FSL_DR_USB
586
587#ifdef CONFIG_HAS_FSL_DR_USB
588#ifdef CONFIG_USB_EHCI_HCD
589#define CONFIG_USB_EHCI_FSL
590#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
591#endif
592#endif
593
594#ifdef CONFIG_MMC
595#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
596#endif
597
598
599#ifndef CONFIG_NOBQFMAN
600#define CONFIG_SYS_BMAN_NUM_PORTALS 10
601#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
602#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
603#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
604#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
605#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
606#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
607#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
608#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
609 CONFIG_SYS_BMAN_CENA_SIZE)
610#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
611#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
612#define CONFIG_SYS_QMAN_NUM_PORTALS 10
613#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
614#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
615#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
616#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
617#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
618#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
619#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
620#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
621 CONFIG_SYS_QMAN_CENA_SIZE)
622#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
623#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
624
625#define CONFIG_SYS_DPAA_FMAN
626#define CONFIG_SYS_DPAA_PME
627
628#define CONFIG_U_QE
629
630
631#if defined(CONFIG_SPIFLASH)
632
633
634
635
636#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
637#elif defined(CONFIG_SDCARD)
638
639
640
641
642
643#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
644#elif defined(CONFIG_MTD_RAW_NAND)
645#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
646#else
647#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
648#endif
649
650#if defined(CONFIG_SPIFLASH)
651#define CONFIG_SYS_QE_FW_ADDR 0x130000
652#elif defined(CONFIG_SDCARD)
653#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
654#elif defined(CONFIG_MTD_RAW_NAND)
655#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
656#else
657#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
658#endif
659
660#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
661#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
662#endif
663
664#ifdef CONFIG_FMAN_ENET
665#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
666#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
667#elif defined(CONFIG_TARGET_T1040D4RDB)
668#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
669#elif defined(CONFIG_TARGET_T1042D4RDB)
670#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
671#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
672#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
673#endif
674
675#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
676#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
677#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
678#else
679#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
680#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
681#endif
682
683
684#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
685#define CONFIG_VSC9953
686#ifdef CONFIG_TARGET_T1040RDB
687#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
688#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
689#else
690#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
691#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
692#endif
693#endif
694
695#define CONFIG_ETHPRIME "FM1@DTSEC4"
696#endif
697
698
699
700
701#define CONFIG_LOADS_ECHO
702#define CONFIG_SYS_LOADS_BAUD_CHANGE
703
704
705
706
707#define CONFIG_SYS_LOAD_ADDR 0x2000000
708
709
710
711
712
713
714#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
715#define CONFIG_SYS_BOOTM_LEN (64 << 20)
716
717#ifdef CONFIG_CMD_KGDB
718#define CONFIG_KGDB_BAUDRATE 230400
719#endif
720
721
722
723
724
725
726
727
728#define CONFIG_ROOTPATH "/opt/nfsroot"
729#define CONFIG_BOOTFILE "uImage"
730#define CONFIG_UBOOTPATH "u-boot.bin"
731
732
733#define CONFIG_LOADADDR 1000000
734
735#define __USB_PHY_TYPE utmi
736#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
737
738#ifdef CONFIG_TARGET_T1040RDB
739#define FDTFILE "t1040rdb/t1040rdb.dtb"
740#elif defined(CONFIG_TARGET_T1042RDB_PI)
741#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
742#elif defined(CONFIG_TARGET_T1042RDB)
743#define FDTFILE "t1042rdb/t1042rdb.dtb"
744#elif defined(CONFIG_TARGET_T1040D4RDB)
745#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
746#elif defined(CONFIG_TARGET_T1042D4RDB)
747#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
748#endif
749
750#ifdef CONFIG_FSL_DIU_FB
751#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
752#else
753#define DIU_ENVIRONMENT
754#endif
755
756#define CONFIG_EXTRA_ENV_SETTINGS \
757 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
758 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
759 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
760 "netdev=eth0\0" \
761 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
762 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
763 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
764 "tftpflash=tftpboot $loadaddr $uboot && " \
765 "protect off $ubootaddr +$filesize && " \
766 "erase $ubootaddr +$filesize && " \
767 "cp.b $loadaddr $ubootaddr $filesize && " \
768 "protect on $ubootaddr +$filesize && " \
769 "cmp.b $loadaddr $ubootaddr $filesize\0" \
770 "consoledev=ttyS0\0" \
771 "ramdiskaddr=2000000\0" \
772 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
773 "fdtaddr=1e00000\0" \
774 "fdtfile=" __stringify(FDTFILE) "\0" \
775 "bdev=sda3\0"
776
777#define CONFIG_LINUX \
778 "setenv bootargs root=/dev/ram rw " \
779 "console=$consoledev,$baudrate $othbootargs;" \
780 "setenv ramdiskaddr 0x02000000;" \
781 "setenv fdtaddr 0x00c00000;" \
782 "setenv loadaddr 0x1000000;" \
783 "bootm $loadaddr $ramdiskaddr $fdtaddr"
784
785#define CONFIG_HDBOOT \
786 "setenv bootargs root=/dev/$bdev rw " \
787 "console=$consoledev,$baudrate $othbootargs;" \
788 "tftp $loadaddr $bootfile;" \
789 "tftp $fdtaddr $fdtfile;" \
790 "bootm $loadaddr - $fdtaddr"
791
792#define CONFIG_NFSBOOTCOMMAND \
793 "setenv bootargs root=/dev/nfs rw " \
794 "nfsroot=$serverip:$rootpath " \
795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
796 "console=$consoledev,$baudrate $othbootargs;" \
797 "tftp $loadaddr $bootfile;" \
798 "tftp $fdtaddr $fdtfile;" \
799 "bootm $loadaddr - $fdtaddr"
800
801#define CONFIG_RAMBOOTCOMMAND \
802 "setenv bootargs root=/dev/ram rw " \
803 "console=$consoledev,$baudrate $othbootargs;" \
804 "tftp $ramdiskaddr $ramdiskfile;" \
805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr $ramdiskaddr $fdtaddr"
808
809#define CONFIG_BOOTCOMMAND CONFIG_LINUX
810
811#include <asm/fsl_secure_boot.h>
812
813#endif
814
