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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <linux/stringify.h>
13
14#define CONFIG_FSL_SATA_V2
15#define CONFIG_PCIE4
16
17#define CONFIG_ICS307_REFCLK_HZ 25000000
18
19#ifdef CONFIG_RAMBOOT_PBL
20#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
21#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
22#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24#else
25#define CONFIG_SPL_FLUSH_IMAGE
26#define CONFIG_SPL_PAD_TO 0x40000
27#define CONFIG_SPL_MAX_SIZE 0x28000
28#define RESET_VECTOR_OFFSET 0x27FFC
29#define BOOT_PAGE_OFFSET 0x27000
30
31#ifdef CONFIG_MTD_RAW_NAND
32#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
33#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
34#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
35#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
36#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
37#endif
38
39#ifdef CONFIG_SDCARD
40#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
41#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
42#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
43#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
44#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
45#ifndef CONFIG_SPL_BUILD
46#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#endif
48#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
49#endif
50
51#ifdef CONFIG_SPL_BUILD
52#define CONFIG_SPL_SKIP_RELOCATE
53#define CONFIG_SPL_COMMON_INIT_DDR
54#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
55#endif
56
57#endif
58#endif
59
60#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
61
62#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
63#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
64 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
65#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
66#endif
67
68#define CONFIG_SRIO_PCIE_BOOT_MASTER
69#define CONFIG_DDR_ECC
70
71#include "t4qds.h"
72
73#if defined(CONFIG_SPIFLASH)
74#elif defined(CONFIG_SDCARD)
75#define CONFIG_SYS_MMC_ENV_DEV 0
76#endif
77
78#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
79#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
80
81#ifndef __ASSEMBLY__
82unsigned long get_board_sys_clk(void);
83unsigned long get_board_ddr_clk(void);
84#endif
85
86
87#define CONFIG_ID_EEPROM
88#define CONFIG_SYS_I2C_EEPROM_NXID
89#define CONFIG_SYS_EEPROM_BUS_NUM 0
90#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
91#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
92
93
94
95
96#define CONFIG_SYS_SPD_BUS_NUM 0
97#define SPD_EEPROM_ADDRESS1 0x51
98#define SPD_EEPROM_ADDRESS2 0x52
99#define SPD_EEPROM_ADDRESS3 0x53
100#define SPD_EEPROM_ADDRESS4 0x54
101#define SPD_EEPROM_ADDRESS5 0x55
102#define SPD_EEPROM_ADDRESS6 0x56
103#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
104#define CONFIG_SYS_SDRAM_SIZE 4096
105
106
107
108
109#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
110#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
111 + 0x8000000) | \
112 CSPR_PORT_SIZE_16 | \
113 CSPR_MSEL_NOR | \
114 CSPR_V)
115#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
116#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
117 CSPR_PORT_SIZE_16 | \
118 CSPR_MSEL_NOR | \
119 CSPR_V)
120#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
121
122#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
123
124#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
125 FTIM0_NOR_TEADC(0x5) | \
126 FTIM0_NOR_TEAHC(0x5))
127#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
128 FTIM1_NOR_TRAD_NOR(0x1A) |\
129 FTIM1_NOR_TSEQRAD_NOR(0x13))
130#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
131 FTIM2_NOR_TCH(0x4) | \
132 FTIM2_NOR_TWPH(0x0E) | \
133 FTIM2_NOR_TWP(0x1c))
134#define CONFIG_SYS_NOR_FTIM3 0x0
135
136#define CONFIG_SYS_FLASH_QUIET_TEST
137#define CONFIG_FLASH_SHOW_PROGRESS 45
138
139#define CONFIG_SYS_MAX_FLASH_BANKS 2
140#define CONFIG_SYS_MAX_FLASH_SECT 1024
141#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
142#define CONFIG_SYS_FLASH_WRITE_TOUT 500
143
144#define CONFIG_SYS_FLASH_EMPTY_INFO
145#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
146 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
147
148#define CONFIG_FSL_QIXIS
149#define QIXIS_BASE 0xffdf0000
150#define QIXIS_LBMAP_SWITCH 6
151#define QIXIS_LBMAP_MASK 0x0f
152#define QIXIS_LBMAP_SHIFT 0
153#define QIXIS_LBMAP_DFLTBANK 0x00
154#define QIXIS_LBMAP_ALTBANK 0x04
155#define QIXIS_RST_CTL_RESET 0x83
156#define QIXIS_RST_FORCE_MEM 0x1
157#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
158#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
159#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
160#define QIXIS_BRDCFG5 0x55
161#define QIXIS_MUX_SDHC 2
162#define QIXIS_MUX_SDHC_WIDTH8 1
163#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
164
165#define CONFIG_SYS_CSPR3_EXT (0xf)
166#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
167 | CSPR_PORT_SIZE_8 \
168 | CSPR_MSEL_GPCM \
169 | CSPR_V)
170#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
171#define CONFIG_SYS_CSOR3 0x0
172
173#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
174 FTIM0_GPCM_TEADC(0x0e) | \
175 FTIM0_GPCM_TEAHC(0x0e))
176#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
177 FTIM1_GPCM_TRAD(0x3f))
178#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
179 FTIM2_GPCM_TCH(0x8) | \
180 FTIM2_GPCM_TWP(0x1f))
181#define CONFIG_SYS_CS3_FTIM3 0x0
182
183
184#define CONFIG_NAND_FSL_IFC
185#define CONFIG_SYS_NAND_BASE 0xff800000
186#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
187
188#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
189#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 \
191 | CSPR_MSEL_NAND \
192 | CSPR_V)
193#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
194
195#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
196 | CSOR_NAND_ECC_DEC_EN \
197 | CSOR_NAND_ECC_MODE_4 \
198 | CSOR_NAND_RAL_3 \
199 | CSOR_NAND_PGS_2K \
200 | CSOR_NAND_SPRZ_64 \
201 | CSOR_NAND_PB(64))
202
203#define CONFIG_SYS_NAND_ONFI_DETECTION
204
205
206#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
207 FTIM0_NAND_TWP(0x18) | \
208 FTIM0_NAND_TWCHT(0x07) | \
209 FTIM0_NAND_TWH(0x0a))
210#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
211 FTIM1_NAND_TWBE(0x39) | \
212 FTIM1_NAND_TRR(0x0e) | \
213 FTIM1_NAND_TRP(0x18))
214#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
215 FTIM2_NAND_TREH(0x0a) | \
216 FTIM2_NAND_TWHRE(0x1e))
217#define CONFIG_SYS_NAND_FTIM3 0x0
218
219#define CONFIG_SYS_NAND_DDR_LAW 11
220
221#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
222#define CONFIG_SYS_MAX_NAND_DEVICE 1
223
224#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
225#define CONFIG_SYS_NAND_MAX_OOBFREE 2
226#define CONFIG_SYS_NAND_MAX_ECCPOS 256
227
228#if defined(CONFIG_MTD_RAW_NAND)
229#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
230#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
231#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
232#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
233#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
234#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
235#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
236#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
237#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
238#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
239#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
240#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
241#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
242#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
243#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
244#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
245#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
246#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
247#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
248#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
249#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
250#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
251#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
252#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
253#else
254#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
255#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
256#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
257#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
258#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
259#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
260#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
261#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
262#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
263#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
264#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
271#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
272#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
273#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
274#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
275#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
276#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
277#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
278#endif
279
280#if defined(CONFIG_RAMBOOT_PBL)
281#define CONFIG_SYS_RAMBOOT
282#endif
283
284
285#ifndef CONFIG_DM_I2C
286#define CONFIG_SYS_I2C
287#else
288#undef CONFIG_SYS_I2C
289#undef CONFIG_SYS_FSL_I2C2_OFFSET
290#undef CONFIG_SYS_FSL_I2C2_SLAVE
291#undef CONFIG_SYS_FSL_I2C2_SPEED
292#undef CONFIG_SYS_FSL_I2C_SLAVE
293#undef CONFIG_SYS_FSL_I2C_SPEED
294#undef CONFIG_SYS_FSL_I2C_OFFSET
295#endif
296
297#define CONFIG_SYS_I2C_FSL
298#define CONFIG_SYS_FSL_I2C_SPEED 100000
299#define CONFIG_SYS_FSL_I2C2_SPEED 100000
300#define I2C_MUX_PCA_ADDR_PRI 0x77
301#define I2C_MUX_PCA_ADDR_SEC 0x76
302
303#define I2C_MUX_CH_DEFAULT 0x8
304#define I2C_MUX_CH_VOL_MONITOR 0xa
305#define I2C_MUX_CH_VSC3316_FS 0xc
306#define I2C_MUX_CH_VSC3316_BS 0xd
307
308
309#define I2C_VOL_MONITOR_ADDR 0x40
310#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
311#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
312#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
313
314
315#define CONFIG_VSC_CROSSBAR
316#define VSC3316_FSM_TX_ADDR 0x70
317#define VSC3316_FSM_RX_ADDR 0x71
318
319
320
321
322
323
324
325
326
327#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
328#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
329#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
330#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
331
332
333
334
335#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
336#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
337#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
338
339
340#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
341#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
342
343
344
345
346#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
347#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
348#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
349 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
350#endif
351
352
353
354
355
356#ifndef CONFIG_NOBQFMAN
357#define CONFIG_SYS_BMAN_NUM_PORTALS 50
358#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
359#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
360#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
361#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
362#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
363#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
364#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
365#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
366 CONFIG_SYS_BMAN_CENA_SIZE)
367#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
368#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
369#define CONFIG_SYS_QMAN_NUM_PORTALS 50
370#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
371#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
372#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
373#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
374#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
375#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
376#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
377#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
378 CONFIG_SYS_QMAN_CENA_SIZE)
379#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
380#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
381
382#define CONFIG_SYS_DPAA_FMAN
383#define CONFIG_SYS_DPAA_PME
384#define CONFIG_SYS_PMAN
385#define CONFIG_SYS_DPAA_DCE
386#define CONFIG_SYS_DPAA_RMAN
387#define CONFIG_SYS_INTERLAKEN
388
389
390#if defined(CONFIG_SPIFLASH)
391
392
393
394
395#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
396#elif defined(CONFIG_SDCARD)
397
398
399
400
401
402#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
403#elif defined(CONFIG_MTD_RAW_NAND)
404#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
405#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
406
407
408
409
410
411
412
413#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
414#else
415#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
416#endif
417#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
418#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
419#endif
420
421#ifdef CONFIG_SYS_DPAA_FMAN
422#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
423#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
424#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
425#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
426#define FM1_10GEC1_PHY_ADDR 0x0
427#define FM1_10GEC2_PHY_ADDR 0x1
428#define FM2_10GEC1_PHY_ADDR 0x2
429#define FM2_10GEC2_PHY_ADDR 0x3
430#endif
431
432
433#ifdef CONFIG_FSL_SATA_V2
434#define CONFIG_SYS_SATA_MAX_DEVICE 2
435#define CONFIG_SATA1
436#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
437#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
438#define CONFIG_SATA2
439#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
440#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
441
442#define CONFIG_LBA48
443#endif
444
445#ifdef CONFIG_FMAN_ENET
446#define CONFIG_ETHPRIME "FM1@DTSEC1"
447#endif
448
449
450
451
452#define CONFIG_USB_EHCI_FSL
453#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
454#define CONFIG_HAS_FSL_DR_USB
455
456#ifdef CONFIG_MMC
457#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
458#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
459#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
460#define CONFIG_ESDHC_DETECT_QUIRK \
461 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
462 IS_SVR_REV(get_svr(), 1, 0))
463#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
464 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
465#endif
466
467
468#define __USB_PHY_TYPE utmi
469
470
471
472
473
474
475
476#ifdef CONFIG_ARCH_T4240
477#define CTRL_INTLV_PREFERED 3way_4KB
478#else
479#define CTRL_INTLV_PREFERED cacheline
480#endif
481
482#define CONFIG_EXTRA_ENV_SETTINGS \
483 "hwconfig=fsl_ddr:" \
484 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
485 "bank_intlv=auto;" \
486 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
487 "netdev=eth0\0" \
488 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
489 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
490 "tftpflash=tftpboot $loadaddr $uboot && " \
491 "protect off $ubootaddr +$filesize && " \
492 "erase $ubootaddr +$filesize && " \
493 "cp.b $loadaddr $ubootaddr $filesize && " \
494 "protect on $ubootaddr +$filesize && " \
495 "cmp.b $loadaddr $ubootaddr $filesize\0" \
496 "consoledev=ttyS0\0" \
497 "ramdiskaddr=2000000\0" \
498 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
499 "fdtaddr=1e00000\0" \
500 "fdtfile=t4240qds/t4240qds.dtb\0" \
501 "bdev=sda3\0"
502
503#define CONFIG_HVBOOT \
504 "setenv bootargs config-addr=0x60000000; " \
505 "bootm 0x01000000 - 0x00f00000"
506
507#define CONFIG_ALU \
508 "setenv bootargs root=/dev/$bdev rw " \
509 "console=$consoledev,$baudrate $othbootargs;" \
510 "cpu 1 release 0x01000000 - - -;" \
511 "cpu 2 release 0x01000000 - - -;" \
512 "cpu 3 release 0x01000000 - - -;" \
513 "cpu 4 release 0x01000000 - - -;" \
514 "cpu 5 release 0x01000000 - - -;" \
515 "cpu 6 release 0x01000000 - - -;" \
516 "cpu 7 release 0x01000000 - - -;" \
517 "go 0x01000000"
518
519#define CONFIG_LINUX \
520 "setenv bootargs root=/dev/ram rw " \
521 "console=$consoledev,$baudrate $othbootargs;" \
522 "setenv ramdiskaddr 0x02000000;" \
523 "setenv fdtaddr 0x00c00000;" \
524 "setenv loadaddr 0x1000000;" \
525 "bootm $loadaddr $ramdiskaddr $fdtaddr"
526
527#define CONFIG_HDBOOT \
528 "setenv bootargs root=/dev/$bdev rw " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "tftp $loadaddr $bootfile;" \
531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr - $fdtaddr"
533
534#define CONFIG_NFSBOOTCOMMAND \
535 "setenv bootargs root=/dev/nfs rw " \
536 "nfsroot=$serverip:$rootpath " \
537 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
538 "console=$consoledev,$baudrate $othbootargs;" \
539 "tftp $loadaddr $bootfile;" \
540 "tftp $fdtaddr $fdtfile;" \
541 "bootm $loadaddr - $fdtaddr"
542
543#define CONFIG_RAMBOOTCOMMAND \
544 "setenv bootargs root=/dev/ram rw " \
545 "console=$consoledev,$baudrate $othbootargs;" \
546 "tftp $ramdiskaddr $ramdiskfile;" \
547 "tftp $loadaddr $bootfile;" \
548 "tftp $fdtaddr $fdtfile;" \
549 "bootm $loadaddr $ramdiskaddr $fdtaddr"
550
551#define CONFIG_BOOTCOMMAND CONFIG_LINUX
552
553#include <asm/fsl_secure_boot.h>
554
555#endif
556
