1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2019 NXP 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#define CONFIG_ARMV7_PSCI_1_0 11 12#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14#define CONFIG_SYS_FSL_CLK 15 16#define CONFIG_SKIP_LOWLEVEL_INIT 17 18#define CONFIG_DEEP_SLEEP 19 20/* 21 * Size of malloc() pool 22 */ 23#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 24 25#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 26#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 27 28#ifndef __ASSEMBLY__ 29unsigned long get_board_sys_clk(void); 30unsigned long get_board_ddr_clk(void); 31#endif 32 33#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 34#define CONFIG_SYS_CLK_FREQ 100000000 35#define CONFIG_DDR_CLK_FREQ 100000000 36#define CONFIG_QIXIS_I2C_ACCESS 37#else 38#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 39#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 40#endif 41 42#ifdef CONFIG_RAMBOOT_PBL 43#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 44#endif 45 46#ifdef CONFIG_SD_BOOT 47#ifdef CONFIG_SD_BOOT_QSPI 48#define CONFIG_SYS_FSL_PBL_RCW \ 49 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 50#else 51#define CONFIG_SYS_FSL_PBL_RCW \ 52 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 53#endif 54 55#define CONFIG_SPL_MAX_SIZE 0x1a000 56#define CONFIG_SPL_STACK 0x1001d000 57#define CONFIG_SPL_PAD_TO 0x1c000 58 59#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 60 CONFIG_SYS_MONITOR_LEN) 61#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62#define CONFIG_SPL_BSS_START_ADDR 0x80100000 63#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64#define CONFIG_SYS_MONITOR_LEN 0xc0000 65#endif 66 67#ifdef CONFIG_NAND_BOOT 68#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 69 70#define CONFIG_SPL_MAX_SIZE 0x1a000 71#define CONFIG_SPL_STACK 0x1001d000 72#define CONFIG_SPL_PAD_TO 0x1c000 73 74#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 75#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 76#define CONFIG_SYS_NAND_PAGE_SIZE 2048 77#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 78#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 79 80#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 81#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 82#define CONFIG_SPL_BSS_START_ADDR 0x80100000 83#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 84#define CONFIG_SYS_MONITOR_LEN 0x80000 85#endif 86 87#define CONFIG_DDR_SPD 88#define SPD_EEPROM_ADDRESS 0x51 89#define CONFIG_SYS_SPD_BUS_NUM 0 90 91#ifndef CONFIG_SYS_FSL_DDR4 92#define CONFIG_SYS_DDR_RAW_TIMING 93#endif 94#define CONFIG_DIMM_SLOTS_PER_CTLR 1 95#define CONFIG_CHIP_SELECTS_PER_CTRL 4 96 97#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 100#define CONFIG_DDR_ECC 101#ifdef CONFIG_DDR_ECC 102#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 103#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 104#endif 105 106/* 107 * IFC Definitions 108 */ 109#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 110#define CONFIG_FSL_IFC 111#define CONFIG_SYS_FLASH_BASE 0x60000000 112#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 113 114#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 115#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 116 CSPR_PORT_SIZE_16 | \ 117 CSPR_MSEL_NOR | \ 118 CSPR_V) 119#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 120#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 121 + 0x8000000) | \ 122 CSPR_PORT_SIZE_16 | \ 123 CSPR_MSEL_NOR | \ 124 CSPR_V) 125#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 126 127#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 128 CSOR_NOR_TRHZ_80) 129#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 130 FTIM0_NOR_TEADC(0x5) | \ 131 FTIM0_NOR_TEAHC(0x5)) 132#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 133 FTIM1_NOR_TRAD_NOR(0x1a) | \ 134 FTIM1_NOR_TSEQRAD_NOR(0x13)) 135#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 136 FTIM2_NOR_TCH(0x4) | \ 137 FTIM2_NOR_TWPH(0xe) | \ 138 FTIM2_NOR_TWP(0x1c)) 139#define CONFIG_SYS_NOR_FTIM3 0 140 141#define CONFIG_SYS_FLASH_QUIET_TEST 142#define CONFIG_FLASH_SHOW_PROGRESS 45 143#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 144#define CONFIG_SYS_WRITE_SWAPPED_DATA 145 146#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 147#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 148#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 150 151#define CONFIG_SYS_FLASH_EMPTY_INFO 152#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 153 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 154 155/* 156 * NAND Flash Definitions 157 */ 158#define CONFIG_NAND_FSL_IFC 159 160#define CONFIG_SYS_NAND_BASE 0x7e800000 161#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 162 163#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 164 165#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 166 | CSPR_PORT_SIZE_8 \ 167 | CSPR_MSEL_NAND \ 168 | CSPR_V) 169#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 170#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 171 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 172 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 173 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 174 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 175 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 176 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 177 178#define CONFIG_SYS_NAND_ONFI_DETECTION 179 180#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 181 FTIM0_NAND_TWP(0x18) | \ 182 FTIM0_NAND_TWCHT(0x7) | \ 183 FTIM0_NAND_TWH(0xa)) 184#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 185 FTIM1_NAND_TWBE(0x39) | \ 186 FTIM1_NAND_TRR(0xe) | \ 187 FTIM1_NAND_TRP(0x18)) 188#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 189 FTIM2_NAND_TREH(0xa) | \ 190 FTIM2_NAND_TWHRE(0x1e)) 191#define CONFIG_SYS_NAND_FTIM3 0x0 192 193#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 194#define CONFIG_SYS_MAX_NAND_DEVICE 1 195 196#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 197#endif 198 199/* 200 * QIXIS Definitions 201 */ 202#define CONFIG_FSL_QIXIS 203 204#ifdef CONFIG_FSL_QIXIS 205#define QIXIS_BASE 0x7fb00000 206#define QIXIS_BASE_PHYS QIXIS_BASE 207#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 208#define QIXIS_LBMAP_SWITCH 6 209#define QIXIS_LBMAP_MASK 0x0f 210#define QIXIS_LBMAP_SHIFT 0 211#define QIXIS_LBMAP_DFLTBANK 0x00 212#define QIXIS_LBMAP_ALTBANK 0x04 213#define QIXIS_PWR_CTL 0x21 214#define QIXIS_PWR_CTL_POWEROFF 0x80 215#define QIXIS_RST_CTL_RESET 0x44 216#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 217#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 218#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 219#define QIXIS_CTL_SYS 0x5 220#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 221#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 222#define QIXIS_RST_FORCE_3 0x45 223#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 224#define QIXIS_PWR_CTL2 0x21 225#define QIXIS_PWR_CTL2_PCTL 0x2 226 227#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 228#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 229 CSPR_PORT_SIZE_8 | \ 230 CSPR_MSEL_GPCM | \ 231 CSPR_V) 232#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 233#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 234 CSOR_NOR_NOR_MODE_AVD_NOR | \ 235 CSOR_NOR_TRHZ_80) 236 237/* 238 * QIXIS Timing parameters for IFC GPCM 239 */ 240#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 241 FTIM0_GPCM_TEADC(0xe) | \ 242 FTIM0_GPCM_TEAHC(0xe)) 243#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 244 FTIM1_GPCM_TRAD(0x1f)) 245#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 246 FTIM2_GPCM_TCH(0xe) | \ 247 FTIM2_GPCM_TWP(0xf0)) 248#define CONFIG_SYS_FPGA_FTIM3 0x0 249#endif 250 251#if defined(CONFIG_NAND_BOOT) 252#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 253#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 254#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 255#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 256#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 257#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 258#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 259#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 260#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 261#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 262#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 263#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 264#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 265#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 266#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 267#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 268#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 269#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 270#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 271#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 272#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 273#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 274#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 275#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 276#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 277#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 278#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 279#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 280#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 281#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 282#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 283#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 284#else 285#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 286#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 287#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 288#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 289#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 290#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 291#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 292#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 293#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 294#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 295#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 296#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 297#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 298#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 299#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 300#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 301#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 302#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 303#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 304#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 305#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 306#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 307#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 308#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 309#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 310#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 311#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 312#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 313#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 314#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 315#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 316#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 317#endif 318 319/* 320 * Serial Port 321 */ 322#ifdef CONFIG_LPUART 323#define CONFIG_LPUART_32B_REG 324#else 325#define CONFIG_SYS_NS16550_SERIAL 326#ifndef CONFIG_DM_SERIAL 327#define CONFIG_SYS_NS16550_REG_SIZE 1 328#endif 329#define CONFIG_SYS_NS16550_CLK get_serial_clock() 330#endif 331 332/* 333 * I2C 334 */ 335#ifndef CONFIG_DM_I2C 336#define CONFIG_SYS_I2C 337#else 338#define CONFIG_I2C_SET_DEFAULT_BUS_NUM 339#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 340#endif 341#define CONFIG_SYS_I2C_MXC 342#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 343#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 344#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 345 346/* EEPROM */ 347#define CONFIG_ID_EEPROM 348#define CONFIG_SYS_I2C_EEPROM_NXID 349#define CONFIG_SYS_EEPROM_BUS_NUM 0 350#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 351#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 352#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 353#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 354 355/* 356 * I2C bus multiplexer 357 */ 358#define I2C_MUX_PCA_ADDR_PRI 0x77 359#define I2C_MUX_CH_DEFAULT 0x8 360#define I2C_MUX_CH_CH7301 0xC 361 362/* 363 * MMC 364 */ 365 366/* DM SPI */ 367#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 368#define CONFIG_DM_SPI_FLASH 369#endif 370 371/* 372 * Video 373 */ 374#ifdef CONFIG_VIDEO_FSL_DCU_FB 375#define CONFIG_VIDEO_LOGO 376#define CONFIG_VIDEO_BMP_LOGO 377 378#define CONFIG_FSL_DIU_CH7301 379#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 380#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 381#define CONFIG_SYS_I2C_DVI_ADDR 0x75 382#endif 383 384/* 385 * eTSEC 386 */ 387 388#ifdef CONFIG_TSEC_ENET 389#define CONFIG_MII_DEFAULT_TSEC 3 390#define CONFIG_TSEC1 1 391#define CONFIG_TSEC1_NAME "eTSEC1" 392#define CONFIG_TSEC2 1 393#define CONFIG_TSEC2_NAME "eTSEC2" 394#define CONFIG_TSEC3 1 395#define CONFIG_TSEC3_NAME "eTSEC3" 396 397#define TSEC1_PHY_ADDR 1 398#define TSEC2_PHY_ADDR 2 399#define TSEC3_PHY_ADDR 3 400 401#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 402#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 403#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 404 405#define TSEC1_PHYIDX 0 406#define TSEC2_PHYIDX 0 407#define TSEC3_PHYIDX 0 408 409#define CONFIG_ETHPRIME "eTSEC1" 410 411#define CONFIG_HAS_ETH0 412#define CONFIG_HAS_ETH1 413#define CONFIG_HAS_ETH2 414 415#define CONFIG_FSL_SGMII_RISER 1 416#define SGMII_RISER_PHY_OFFSET 0x1b 417 418#ifdef CONFIG_FSL_SGMII_RISER 419#define CONFIG_SYS_TBIPA_VALUE 8 420#endif 421 422#endif 423 424/* PCIe */ 425#define CONFIG_PCIE1 /* PCIE controller 1 */ 426#define CONFIG_PCIE2 /* PCIE controller 2 */ 427 428#ifdef CONFIG_PCI 429#define CONFIG_PCI_SCAN_SHOW 430#endif 431 432#define CONFIG_CMDLINE_TAG 433 434#define CONFIG_PEN_ADDR_BIG_ENDIAN 435#define CONFIG_LAYERSCAPE_NS_ACCESS 436#define CONFIG_SMP_PEN_ADDR 0x01ee0200 437#define COUNTER_FREQUENCY 12500000 438 439#define CONFIG_HWCONFIG 440#define HWCONFIG_BUFFER_SIZE 256 441 442#define CONFIG_FSL_DEVICE_DISABLE 443 444 445#define CONFIG_SYS_QE_FW_ADDR 0x60940000 446 447#ifdef CONFIG_LPUART 448#define CONFIG_EXTRA_ENV_SETTINGS \ 449 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 450 "initrd_high=0xffffffff\0" \ 451 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 452#else 453#define CONFIG_EXTRA_ENV_SETTINGS \ 454 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 455 "initrd_high=0xffffffff\0" \ 456 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 457#endif 458 459/* 460 * Miscellaneous configurable options 461 */ 462#define CONFIG_SYS_BOOTMAPSZ (256 << 20) 463 464#define CONFIG_SYS_LOAD_ADDR 0x82000000 465 466#define CONFIG_LS102XA_STREAM_ID 467 468#define CONFIG_SYS_INIT_SP_OFFSET \ 469 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 470#define CONFIG_SYS_INIT_SP_ADDR \ 471 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 472 473#ifdef CONFIG_SPL_BUILD 474#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 475#else 476#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 477#endif 478 479/* 480 * Environment 481 */ 482#define CONFIG_ENV_OVERWRITE 483 484#if defined(CONFIG_SD_BOOT) 485#define CONFIG_SYS_MMC_ENV_DEV 0 486#endif 487 488#include <asm/fsl_secure_boot.h> 489#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 490 491#endif 492