LXR uboot/include/configs/ls1043a

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2015 Freescale Semiconductor
   4 * Copyright (C) 2019 NXP
   5 */
   6
   7#ifndef __LS1043A_COMMON_H
   8#define __LS1043A_COMMON_H
   9
  10/* SPL build */
  11#ifdef CONFIG_SPL_BUILD
  12#define SPL_NO_FMAN
  13#define SPL_NO_DSPI
  14#define SPL_NO_PCIE
  15#define SPL_NO_ENV
  16#define SPL_NO_MISC
  17#define SPL_NO_USB
  18#define SPL_NO_SATA
  19#define SPL_NO_QE
  20#define SPL_NO_EEPROM
  21#endif
  22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  23#define SPL_NO_MMC
  24#endif
  25#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  26#define SPL_NO_IFC
  27#endif
  28
  29#define CONFIG_REMAKE_ELF
  30#define CONFIG_GICV2
  31
  32#include <asm/arch/stream_id_lsch2.h>
  33#include <asm/arch/config.h>
  34
  35/* Link Definitions */
  36#ifdef CONFIG_TFABOOT
  37#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
  38#else
  39#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  40#endif
  41
  42#define CONFIG_SKIP_LOWLEVEL_INIT
  43
  44#define CONFIG_VERY_BIG_RAM
  45#define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  46#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  47#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  48#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  49
  50#define CPU_RELEASE_ADDR               secondary_boot_func
  51
  52/* Generic Timer Definitions */
  53#define COUNTER_FREQUENCY               25000000        /* 25MHz */
  54
  55/* Size of malloc() pool */
  56#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  57
  58/* Serial Port */
  59#define CONFIG_SYS_NS16550_SERIAL
  60#define CONFIG_SYS_NS16550_REG_SIZE     1
  61#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  62
  63#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  64
  65/* SD boot SPL */
  66#ifdef CONFIG_SD_BOOT
  67
  68#define CONFIG_SPL_MAX_SIZE             0x17000
  69#define CONFIG_SPL_STACK                0x1001e000
  70#define CONFIG_SPL_PAD_TO               0x1d000
  71
  72#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  73                                        CONFIG_SPL_BSS_MAX_SIZE)
  74#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  75#define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  76#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  77
  78#ifdef CONFIG_NXP_ESBC
  79#define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  80/*
  81 * HDR would be appended at end of image and copied to DDR along
  82 * with U-Boot image. Here u-boot max. size is 512K. So if binary
  83 * size increases then increase this size in case of secure boot as
  84 * it uses raw u-boot image instead of fit image.
  85 */
  86#define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  87#else
  88#define CONFIG_SYS_MONITOR_LEN          0x100000
  89#endif /* ifdef CONFIG_NXP_ESBC */
  90#endif
  91
  92/* NAND SPL */
  93#ifdef CONFIG_NAND_BOOT
  94#define CONFIG_SPL_PBL_PAD
  95#define CONFIG_SPL_MAX_SIZE             0x1a000
  96#define CONFIG_SPL_STACK                0x1001d000
  97#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  98#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  99#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 100#define CONFIG_SPL_BSS_START_ADDR       0x80100000
 101#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 102#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 103
 104#ifdef CONFIG_NXP_ESBC
 105#define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 106#endif /* ifdef CONFIG_NXP_ESBC */
 107
 108#ifdef CONFIG_U_BOOT_HDR_SIZE
 109/*
 110 * HDR would be appended at end of image and copied to DDR along
 111 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 112 * size increases then increase this size in case of secure boot as
 113 * it uses raw u-boot image instead of fit image.
 114 */
 115#define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 116#else
 117#define CONFIG_SYS_MONITOR_LEN          0x100000
 118#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 119
 120#endif
 121
 122/* IFC */
 123#ifndef SPL_NO_IFC
 124#if defined(CONFIG_TFABOOT) || \
 125        (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
 126#define CONFIG_FSL_IFC
 127/*
 128 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 129 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 130 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 131 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 132 */
 133#define CONFIG_SYS_FLASH_BASE                   0x60000000
 134#define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 135#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 136
 137#ifdef CONFIG_MTD_NOR_FLASH
 138#define CONFIG_SYS_FLASH_QUIET_TEST
 139#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 140#endif
 141#endif
 142#endif
 143
 144/* I2C */
 145#ifndef CONFIG_DM_I2C
 146#define CONFIG_SYS_I2C
 147#define CONFIG_SYS_I2C_MXC
 148#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 149#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 150#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 151#define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
 152#else
 153#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 154#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 155#endif
 156
 157/* PCIe */
 158#ifndef SPL_NO_PCIE
 159#define CONFIG_PCIE1            /* PCIE controller 1 */
 160#define CONFIG_PCIE2            /* PCIE controller 2 */
 161#define CONFIG_PCIE3            /* PCIE controller 3 */
 162
 163#ifdef CONFIG_PCI
 164#define CONFIG_PCI_SCAN_SHOW
 165#endif
 166#endif
 167
 168/*  MMC  */
 169#ifndef SPL_NO_MMC
 170#ifdef CONFIG_MMC
 171#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 172#endif
 173#endif
 174
 175/*  DSPI  */
 176#ifndef SPL_NO_DSPI
 177#define CONFIG_FSL_DSPI
 178#ifdef CONFIG_FSL_DSPI
 179#define CONFIG_DM_SPI_FLASH
 180#define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 181#define CONFIG_SPI_FLASH_SST            /* cs1 */
 182#define CONFIG_SPI_FLASH_EON            /* cs2 */
 183#endif
 184#endif
 185
 186/* FMan ucode */
 187#ifndef SPL_NO_FMAN
 188#define CONFIG_SYS_DPAA_FMAN
 189#ifdef CONFIG_SYS_DPAA_FMAN
 190#define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 191
 192#ifdef CONFIG_TFABOOT
 193#define CONFIG_SYS_FMAN_FW_ADDR         0x900000
 194#define CONFIG_SYS_QE_FW_ADDR           0x940000
 195
 196
 197#else
 198#ifdef CONFIG_NAND_BOOT
 199/* Store Fman ucode at offeset 0x900000(72 blocks). */
 200#define CONFIG_SYS_FMAN_FW_ADDR         (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 201#elif defined(CONFIG_SD_BOOT)
 202/*
 203 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 204 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 205 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
 206 */
 207#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x4800)
 208#define CONFIG_SYS_QE_FW_ADDR           (512 * 0x4A00)
 209#elif defined(CONFIG_QSPI_BOOT)
 210#define CONFIG_SYS_FMAN_FW_ADDR         0x40900000
 211#else
 212/* FMan fireware Pre-load address */
 213#define CONFIG_SYS_FMAN_FW_ADDR         0x60900000
 214#define CONFIG_SYS_QE_FW_ADDR           0x60940000
 215#endif
 216#endif
 217#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 218#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 219#endif
 220#endif
 221
 222/* Miscellaneous configurable options */
 223#define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 224
 225#define CONFIG_HWCONFIG
 226#define HWCONFIG_BUFFER_SIZE            128
 227
 228#ifndef SPL_NO_MISC
 229#ifndef CONFIG_SPL_BUILD
 230#define BOOT_TARGET_DEVICES(func) \
 231        func(MMC, mmc, 0) \
 232        func(USB, usb, 0) \
 233        func(DHCP, dhcp, na)
 234#include <config_distro_bootcmd.h>
 235#endif
 236
 237/* Initial environment variables */
 238#define CONFIG_EXTRA_ENV_SETTINGS               \
 239        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 240        "fdt_high=0xffffffffffffffff\0"         \
 241        "initrd_high=0xffffffffffffffff\0"      \
 242        "fdt_addr=0x64f00000\0"                 \
 243        "kernel_addr=0x61000000\0"              \
 244        "scriptaddr=0x80000000\0"               \
 245        "scripthdraddr=0x80080000\0"            \
 246        "fdtheader_addr_r=0x80100000\0"         \
 247        "kernelheader_addr_r=0x80200000\0"      \
 248        "kernel_addr_r=0x81000000\0"            \
 249        "kernel_start=0x1000000\0"              \
 250        "kernelheader_start=0x800000\0"         \
 251        "fdt_addr_r=0x90000000\0"               \
 252        "load_addr=0xa0000000\0"                \
 253        "kernelheader_addr=0x60800000\0"        \
 254        "kernel_size=0x2800000\0"               \
 255        "kernelheader_size=0x40000\0"           \
 256        "kernel_addr_sd=0x8000\0"               \
 257        "kernel_size_sd=0x14000\0"              \
 258        "kernelhdr_addr_sd=0x4000\0"            \
 259        "kernelhdr_size_sd=0x10\0"              \
 260        "console=ttyS0,115200\0"                \
 261        "boot_os=y\0"                           \
 262        "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"        \
 263        BOOTENV                                 \
 264        "boot_scripts=ls1043ardb_boot.scr\0"    \
 265        "boot_script_hdr=hdr_ls1043ardb_bs.out\0"       \
 266        "scan_dev_for_boot_part="               \
 267                "part list ${devtype} ${devnum} devplist; "     \
 268                "env exists devplist || setenv devplist 1; "    \
 269                "for distro_bootpart in ${devplist}; do "       \
 270                        "if fstype ${devtype} "                 \
 271                                "${devnum}:${distro_bootpart} " \
 272                                "bootfstype; then "             \
 273                                "run scan_dev_for_boot; "       \
 274                        "fi; "                                  \
 275                "done\0"                        \
 276        "boot_a_script="                                        \
 277                "load ${devtype} ${devnum}:${distro_bootpart} " \
 278                        "${scriptaddr} ${prefix}${script}; "    \
 279                "env exists secureboot && load ${devtype} "     \
 280                        "${devnum}:${distro_bootpart} "         \
 281                        "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 282                        "env exists secureboot "        \
 283                        "&& esbc_validate ${scripthdraddr};"    \
 284                "source ${scriptaddr}\0"                        \
 285        "qspi_bootcmd=echo Trying load from qspi..;"    \
 286                "sf probe && sf read $load_addr "       \
 287                "$kernel_start $kernel_size; env exists secureboot "    \
 288                "&& sf read $kernelheader_addr_r $kernelheader_start "  \
 289                "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 290                "bootm $load_addr#$board\0"     \
 291        "nor_bootcmd=echo Trying load from nor..;"      \
 292                "cp.b $kernel_addr $load_addr " \
 293                "$kernel_size; env exists secureboot "  \
 294                "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 295                "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 296                "bootm $load_addr#$board\0"         \
 297        "nand_bootcmd=echo Trying load from NAND..;"    \
 298                "nand info; nand read $load_addr "      \
 299                "$kernel_start $kernel_size; env exists secureboot "    \
 300                "&& nand read $kernelheader_addr_r $kernelheader_start "        \
 301                "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 302                "bootm $load_addr#$board\0"     \
 303        "sd_bootcmd=echo Trying load from SD ..;"       \
 304                "mmcinfo; mmc read $load_addr "         \
 305                "$kernel_addr_sd $kernel_size_sd && "     \
 306                "env exists secureboot && mmc read $kernelheader_addr_r "               \
 307                "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 308                " && esbc_validate ${kernelheader_addr_r};"     \
 309                "bootm $load_addr#$board\0"
 310
 311
 312#undef CONFIG_BOOTCOMMAND
 313#ifdef CONFIG_TFABOOT
 314#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 315                           "env exists secureboot && esbc_halt;"
 316#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
 317                           "env exists secureboot && esbc_halt;"
 318#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 319                           "env exists secureboot && esbc_halt;"
 320#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 321                           "env exists secureboot && esbc_halt;"
 322#else
 323#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 324#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 325                           "env exists secureboot && esbc_halt;"
 326#elif defined(CONFIG_SD_BOOT)
 327#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
 328                           "env exists secureboot && esbc_halt;"
 329#else
 330#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 331                           "env exists secureboot && esbc_halt;"
 332#endif
 333#endif
 334#endif
 335
 336/* Monitor Command Prompt */
 337#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 338
 339#define CONFIG_SYS_MAXARGS              64      /* max command args */
 340
 341#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 342
 343#include <asm/arch/soc.h>
 344
 345#endif /* __LS1043A_COMMON_H */
 346