1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017, 2020 NXP 4 */ 5 6#ifndef __LS1088A_QDS_H 7#define __LS1088A_QDS_H 8 9#include "ls1088a_common.h" 10 11 12#ifndef __ASSEMBLY__ 13unsigned long get_board_sys_clk(void); 14unsigned long get_board_ddr_clk(void); 15#endif 16 17#ifdef CONFIG_TFABOOT 18#define CONFIG_SYS_MMC_ENV_DEV 0 19 20#define CONFIG_MISC_INIT_R 21#else 22#if defined(CONFIG_QSPI_BOOT) 23#elif defined(CONFIG_SD_BOOT) 24#define CONFIG_SYS_MMC_ENV_DEV 0 25#endif 26#endif 27 28#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 29#define CONFIG_QIXIS_I2C_ACCESS 30#define SYS_NO_FLASH 31 32#define CONFIG_SYS_CLK_FREQ 100000000 33#define CONFIG_DDR_CLK_FREQ 100000000 34#else 35#define CONFIG_QIXIS_I2C_ACCESS 36#ifndef CONFIG_DM_I2C 37#define CONFIG_SYS_I2C_EARLY_INIT 38#endif 39#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 40#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 41#endif 42 43#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 44#define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 46#define CONFIG_DIMM_SLOTS_PER_CTLR 1 47 48#define CONFIG_DDR_SPD 49#define CONFIG_DDR_ECC 50#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 51#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 52#define SPD_EEPROM_ADDRESS 0x51 53#define CONFIG_SYS_SPD_BUS_NUM 0 54 55 56/* 57 * IFC Definitions 58 */ 59#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 60#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 61#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 62#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 63 64#define CONFIG_SYS_NOR0_CSPR \ 65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 66 CSPR_PORT_SIZE_16 | \ 67 CSPR_MSEL_NOR | \ 68 CSPR_V) 69#define CONFIG_SYS_NOR0_CSPR_EARLY \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 71 CSPR_PORT_SIZE_16 | \ 72 CSPR_MSEL_NOR | \ 73 CSPR_V) 74#define CONFIG_SYS_NOR1_CSPR \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 76 CSPR_PORT_SIZE_16 | \ 77 CSPR_MSEL_NOR | \ 78 CSPR_V) 79#define CONFIG_SYS_NOR1_CSPR_EARLY \ 80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 81 CSPR_PORT_SIZE_16 | \ 82 CSPR_MSEL_NOR | \ 83 CSPR_V) 84#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 85#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 86 FTIM0_NOR_TEADC(0x5) | \ 87 FTIM0_NOR_TAVDS(0x6) | \ 88 FTIM0_NOR_TEAHC(0x5)) 89#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 90 FTIM1_NOR_TRAD_NOR(0x1a) | \ 91 FTIM1_NOR_TSEQRAD_NOR(0x13)) 92#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 93 FTIM2_NOR_TCH(0x8) | \ 94 FTIM2_NOR_TWPH(0xe) | \ 95 FTIM2_NOR_TWP(0x1c)) 96#define CONFIG_SYS_NOR_FTIM3 0x04000000 97#define CONFIG_SYS_IFC_CCR 0x01000000 98 99#ifndef SYS_NO_FLASH 100#define CONFIG_SYS_FLASH_QUIET_TEST 101#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 102 103#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 104#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 105#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 106#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 107 108#define CONFIG_SYS_FLASH_EMPTY_INFO 109#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 110 CONFIG_SYS_FLASH_BASE + 0x40000000} 111#endif 112#endif 113 114#define CONFIG_NAND_FSL_IFC 115#define CONFIG_SYS_NAND_MAX_ECCPOS 256 116#define CONFIG_SYS_NAND_MAX_OOBFREE 2 117 118#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 119#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 120 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 121 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 122 | CSPR_V) 123#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 124 125#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 126 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 127 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 128 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 129 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 130 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 131 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 132 133#define CONFIG_SYS_NAND_ONFI_DETECTION 134 135/* ONFI NAND Flash mode0 Timing Params */ 136#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 137 FTIM0_NAND_TWP(0x18) | \ 138 FTIM0_NAND_TWCHT(0x07) | \ 139 FTIM0_NAND_TWH(0x0a)) 140#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 141 FTIM1_NAND_TWBE(0x39) | \ 142 FTIM1_NAND_TRR(0x0e) | \ 143 FTIM1_NAND_TRP(0x18)) 144#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 145 FTIM2_NAND_TREH(0x0a) | \ 146 FTIM2_NAND_TWHRE(0x1e)) 147#define CONFIG_SYS_NAND_FTIM3 0x0 148 149#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 150#define CONFIG_SYS_MAX_NAND_DEVICE 1 151#define CONFIG_MTD_NAND_VERIFY_WRITE 152 153#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 154 155#define CONFIG_FSL_QIXIS 156#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 157#define QIXIS_LBMAP_SWITCH 6 158#define QIXIS_QMAP_MASK 0xe0 159#define QIXIS_QMAP_SHIFT 5 160#define QIXIS_LBMAP_MASK 0x0f 161#define QIXIS_LBMAP_SHIFT 0 162#define QIXIS_LBMAP_DFLTBANK 0x0e 163#define QIXIS_LBMAP_ALTBANK 0x2e 164#define QIXIS_LBMAP_SD 0x00 165#define QIXIS_LBMAP_EMMC 0x00 166#define QIXIS_LBMAP_IFC 0x00 167#define QIXIS_LBMAP_SD_QSPI 0x0e 168#define QIXIS_LBMAP_QSPI 0x0e 169#define QIXIS_RCW_SRC_IFC 0x25 170#define QIXIS_RCW_SRC_SD 0x40 171#define QIXIS_RCW_SRC_EMMC 0x41 172#define QIXIS_RCW_SRC_QSPI 0x62 173#define QIXIS_RST_CTL_RESET 0x41 174#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 175#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 176#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 177#define QIXIS_RST_FORCE_MEM 0x01 178#define QIXIS_STAT_PRES1 0xb 179#define QIXIS_SDID_MASK 0x07 180#define QIXIS_ESDHC_NO_ADAPTER 0x7 181 182#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 183#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 184 | CSPR_PORT_SIZE_8 \ 185 | CSPR_MSEL_GPCM \ 186 | CSPR_V) 187#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 188 | CSPR_PORT_SIZE_8 \ 189 | CSPR_MSEL_GPCM \ 190 | CSPR_V) 191 192#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 193#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 194#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 195#else 196#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 197#endif 198/* QIXIS Timing parameters*/ 199#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 200 FTIM0_GPCM_TEADC(0x0e) | \ 201 FTIM0_GPCM_TEAHC(0x0e)) 202#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 203 FTIM1_GPCM_TRAD(0x3f)) 204#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 205 FTIM2_GPCM_TCH(0xf) | \ 206 FTIM2_GPCM_TWP(0x3E)) 207#define SYS_FPGA_CS_FTIM3 0x0 208 209#ifdef CONFIG_TFABOOT 210#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 211#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 212#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 213#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 214#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 215#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 216#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 217#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 218#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 219#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 220#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 221#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 222#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 223#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 224#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 225#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 226#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 227#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 228#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 229#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 230#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 231#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 232#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 233#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 234#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 235#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 236#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 237#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 238#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 239#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 240#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 241#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 242#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 243#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 244#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 245#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 246#else 247#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 248#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 249#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 250#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 251#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 252#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 253#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 254#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 255#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 256#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 257#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 258#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 259#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 260#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 261#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 262#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 263#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 264#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 265#else 266#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 267#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 268#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 269#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 270#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 271#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 272#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 273#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 274#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 275#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 276#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 277#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 278#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 279#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 280#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 281#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 282#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 283#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 284#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 285#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 286#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 287#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 288#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 289#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 290#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 291#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 292#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 293#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 294#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 295#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 296#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 297#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 298#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 299#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 300#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 301#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 302#endif 303#endif 304 305#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 306 307/* 308 * I2C bus multiplexer 309 */ 310#define I2C_MUX_PCA_ADDR_PRI 0x77 311#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 312#define I2C_RETIMER_ADDR 0x18 313#define I2C_RETIMER_ADDR2 0x19 314#define I2C_MUX_CH_DEFAULT 0x8 315#define I2C_MUX_CH5 0xD 316 317#define I2C_MUX_CH_VOL_MONITOR 0xA 318 319/* Voltage monitor on channel 2*/ 320#define I2C_VOL_MONITOR_ADDR 0x63 321#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 322#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 323#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 324#define I2C_SVDD_MONITOR_ADDR 0x4F 325 326#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 327#define CONFIG_VID 328 329/* The lowest and highest voltage allowed for LS1088AQDS */ 330#define VDD_MV_MIN 819 331#define VDD_MV_MAX 1212 332 333#define CONFIG_VOL_MONITOR_LTC3882_SET 334#define CONFIG_VOL_MONITOR_LTC3882_READ 335 336/* PM Bus commands code for LTC3882*/ 337#define PMBUS_CMD_PAGE 0x0 338#define PMBUS_CMD_READ_VOUT 0x8B 339#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 340#define PMBUS_CMD_VOUT_COMMAND 0x21 341 342#define PWM_CHANNEL0 0x0 343 344/* 345* RTC configuration 346*/ 347#define RTC 348#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 349 350/* EEPROM */ 351#define CONFIG_ID_EEPROM 352#define CONFIG_SYS_I2C_EEPROM_NXID 353#define CONFIG_SYS_EEPROM_BUS_NUM 0 354#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 355#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 356#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 357#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 358 359#ifdef CONFIG_FSL_DSPI 360#define CONFIG_SPI_FLASH_STMICRO 361#define CONFIG_SPI_FLASH_SST 362#define CONFIG_SPI_FLASH_EON 363#if !defined(CONFIG_TFABOOT) && \ 364 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 365#endif 366#endif 367 368#ifdef CONFIG_SPL_BUILD 369#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 370#else 371#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 372#endif 373 374#define CONFIG_FSL_MEMAC 375 376/* MMC */ 377#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 378#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 379 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 380 381/* Initial environment variables */ 382#ifdef CONFIG_NXP_ESBC 383#undef CONFIG_EXTRA_ENV_SETTINGS 384#define CONFIG_EXTRA_ENV_SETTINGS \ 385 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 386 "loadaddr=0x90100000\0" \ 387 "kernel_addr=0x100000\0" \ 388 "ramdisk_addr=0x800000\0" \ 389 "ramdisk_size=0x2000000\0" \ 390 "fdt_high=0xa0000000\0" \ 391 "initrd_high=0xffffffffffffffff\0" \ 392 "kernel_start=0x1000000\0" \ 393 "kernel_load=0xa0000000\0" \ 394 "kernel_size=0x2800000\0" \ 395 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 396 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ 397 "sf read 0xa0e00000 0xe00000 0x100000;" \ 398 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ 399 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 400 "mcmemsize=0x70000000 \0" 401#else /* if !(CONFIG_NXP_ESBC) */ 402#ifdef CONFIG_TFABOOT 403#define QSPI_MC_INIT_CMD \ 404 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 405 "sf read 0x80100000 0xE00000 0x100000;" \ 406 "fsl_mc start mc 0x80000000 0x80100000\0" 407#define SD_MC_INIT_CMD \ 408 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 409 "mmc read 0x80100000 0x7000 0x800;" \ 410 "fsl_mc start mc 0x80000000 0x80100000\0" 411#define IFC_MC_INIT_CMD \ 412 "fsl_mc start mc 0x580A00000 0x580E00000\0" 413 414#undef CONFIG_EXTRA_ENV_SETTINGS 415#define CONFIG_EXTRA_ENV_SETTINGS \ 416 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 417 "loadaddr=0x90100000\0" \ 418 "kernel_addr=0x100000\0" \ 419 "kernel_addr_sd=0x800\0" \ 420 "ramdisk_addr=0x800000\0" \ 421 "ramdisk_size=0x2000000\0" \ 422 "fdt_high=0xa0000000\0" \ 423 "initrd_high=0xffffffffffffffff\0" \ 424 "kernel_start=0x1000000\0" \ 425 "kernel_start_sd=0x8000\0" \ 426 "kernel_load=0xa0000000\0" \ 427 "kernel_size=0x2800000\0" \ 428 "kernel_size_sd=0x14000\0" \ 429 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 430 "sf read 0x80100000 0xE00000 0x100000;" \ 431 "fsl_mc start mc 0x80000000 0x80100000\0" \ 432 "mcmemsize=0x70000000 \0" \ 433 "BOARD=ls1088aqds\0" \ 434 "scriptaddr=0x80000000\0" \ 435 "scripthdraddr=0x80080000\0" \ 436 BOOTENV \ 437 "boot_scripts=ls1088aqds_boot.scr\0" \ 438 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ 439 "scan_dev_for_boot_part=" \ 440 "part list ${devtype} ${devnum} devplist; " \ 441 "env exists devplist || setenv devplist 1; " \ 442 "for distro_bootpart in ${devplist}; do " \ 443 "if fstype ${devtype} " \ 444 "${devnum}:${distro_bootpart} " \ 445 "bootfstype; then " \ 446 "run scan_dev_for_boot; " \ 447 "fi; " \ 448 "done\0" \ 449 "boot_a_script=" \ 450 "load ${devtype} ${devnum}:${distro_bootpart} " \ 451 "${scriptaddr} ${prefix}${script}; " \ 452 "env exists secureboot && load ${devtype} " \ 453 "${devnum}:${distro_bootpart} " \ 454 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ 455 "env exists secureboot " \ 456 "&& esbc_validate ${scripthdraddr};" \ 457 "source ${scriptaddr}\0" \ 458 "qspi_bootcmd=echo Trying load from qspi..; " \ 459 "sf probe 0:0; " \ 460 "sf read 0x80001000 0xd00000 0x100000; " \ 461 "fsl_mc lazyapply dpl 0x80001000 && " \ 462 "sf read $kernel_load $kernel_start " \ 463 "$kernel_size && bootm $kernel_load#$BOARD\0" \ 464 "sd_bootcmd=echo Trying load from sd card..; " \ 465 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ 466 "fsl_mc lazyapply dpl 0x80001000 && " \ 467 "mmc read $kernel_load $kernel_start_sd " \ 468 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ 469 "nor_bootcmd=echo Trying load from nor..; " \ 470 "fsl_mc lazyapply dpl 0x580d00000 && " \ 471 "cp.b $kernel_start $kernel_load " \ 472 "$kernel_size && bootm $kernel_load#$BOARD\0" 473#else 474#if defined(CONFIG_QSPI_BOOT) 475#undef CONFIG_EXTRA_ENV_SETTINGS 476#define CONFIG_EXTRA_ENV_SETTINGS \ 477 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 478 "loadaddr=0x90100000\0" \ 479 "kernel_addr=0x100000\0" \ 480 "ramdisk_addr=0x800000\0" \ 481 "ramdisk_size=0x2000000\0" \ 482 "fdt_high=0xa0000000\0" \ 483 "initrd_high=0xffffffffffffffff\0" \ 484 "kernel_start=0x1000000\0" \ 485 "kernel_load=0xa0000000\0" \ 486 "kernel_size=0x2800000\0" \ 487 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 488 "sf read 0x80100000 0xE00000 0x100000;" \ 489 "fsl_mc start mc 0x80000000 0x80100000\0" \ 490 "mcmemsize=0x70000000 \0" 491#elif defined(CONFIG_SD_BOOT) 492#undef CONFIG_EXTRA_ENV_SETTINGS 493#define CONFIG_EXTRA_ENV_SETTINGS \ 494 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 495 "loadaddr=0x90100000\0" \ 496 "kernel_addr=0x800\0" \ 497 "ramdisk_addr=0x800000\0" \ 498 "ramdisk_size=0x2000000\0" \ 499 "fdt_high=0xa0000000\0" \ 500 "initrd_high=0xffffffffffffffff\0" \ 501 "kernel_start=0x8000\0" \ 502 "kernel_load=0xa0000000\0" \ 503 "kernel_size=0x14000\0" \ 504 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 505 "mmc read 0x80100000 0x7000 0x800;" \ 506 "fsl_mc start mc 0x80000000 0x80100000\0" \ 507 "mcmemsize=0x70000000 \0" 508#else /* NOR BOOT */ 509#undef CONFIG_EXTRA_ENV_SETTINGS 510#define CONFIG_EXTRA_ENV_SETTINGS \ 511 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 512 "loadaddr=0x90100000\0" \ 513 "kernel_addr=0x100000\0" \ 514 "ramdisk_addr=0x800000\0" \ 515 "ramdisk_size=0x2000000\0" \ 516 "fdt_high=0xa0000000\0" \ 517 "initrd_high=0xffffffffffffffff\0" \ 518 "kernel_start=0x1000000\0" \ 519 "kernel_load=0xa0000000\0" \ 520 "kernel_size=0x2800000\0" \ 521 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 522 "mcmemsize=0x70000000 \0" 523#endif 524#endif /* CONFIG_TFABOOT */ 525#endif /* CONFIG_NXP_ESBC */ 526 527#ifdef CONFIG_TFABOOT 528#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 529 "env exists secureboot && esbc_halt;;" 530#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 531 "env exists secureboot && esbc_halt;;" 532#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 533 "env exists secureboot && esbc_halt;;" 534#endif 535 536#ifdef CONFIG_FSL_MC_ENET 537#define CONFIG_FSL_MEMAC 538#define RGMII_PHY1_ADDR 0x1 539#define RGMII_PHY2_ADDR 0x2 540#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 541#define SGMII_CARD_PORT2_PHY_ADDR 0x1d 542#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 543#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 544 545#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 546#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 547#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 548#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 549#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 550#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 551#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 552#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 553#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 554#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 555#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 556#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 557#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 558#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 559#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 560#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 561 562#define CONFIG_ETHPRIME "DPMAC1@xgmii" 563#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 564 565#endif 566 567#define BOOT_TARGET_DEVICES(func) \ 568 func(USB, usb, 0) \ 569 func(MMC, mmc, 0) \ 570 func(SCSI, scsi, 0) \ 571 func(DHCP, dhcp, na) 572#include <config_distro_bootcmd.h> 573 574#include <asm/fsl_secure_boot.h> 575 576#endif /* __LS1088A_QDS_H */ 577