1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 4 * 5 * (C) Copyright 2004 6 * Texas Instruments. 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Kshitij Gupta <kshitij@ti.com> 9 * 10 * Configuration settings for the Freescale i.MX31 PDK board. 11 */ 12 13#ifndef __CONFIG_H 14#define __CONFIG_H 15 16#include <asm/arch/imx-regs.h> 17 18/* High Level Configuration Options */ 19#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 20#define CONFIG_SETUP_MEMORY_TAGS 21#define CONFIG_INITRD_TAG 22 23#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 24 25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26#define CONFIG_SPL_MAX_SIZE 2048 27 28#ifndef CONFIG_SPL_BUILD 29#define CONFIG_SKIP_LOWLEVEL_INIT 30#endif 31 32/* 33 * Size of malloc() pool 34 */ 35#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 36 37/* 38 * Hardware drivers 39 */ 40 41#define CONFIG_MXC_UART 42#define CONFIG_MXC_UART_BASE UART1_BASE 43 44/* PMIC Controller */ 45#define CONFIG_POWER 46#define CONFIG_POWER_SPI 47#define CONFIG_POWER_FSL 48#define CONFIG_FSL_PMIC_BUS 1 49#define CONFIG_FSL_PMIC_CS 2 50#define CONFIG_FSL_PMIC_CLK 1000000 51#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 52#define CONFIG_FSL_PMIC_BITLEN 32 53#define CONFIG_RTC_MC13XXX 54 55/* allow to overwrite serial and ethaddr */ 56#define CONFIG_ENV_OVERWRITE 57 58#define CONFIG_EXTRA_ENV_SETTINGS \ 59 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 60 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 61 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 62 "bootcmd=run bootcmd_net\0" \ 63 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 64 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 65 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 66 "nand erase 0x0 0x40000; " \ 67 "nand write 0x81000000 0x0 0x40000\0" 68 69/* 70 * Miscellaneous configurable options 71 */ 72 73/* memtest works on */ 74 75/* default load address */ 76#define CONFIG_SYS_LOAD_ADDR 0x81000000 77 78/*----------------------------------------------------------------------- 79 * Physical Memory Map 80 */ 81#define PHYS_SDRAM_1 CSD0_BASE 82#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 83 84#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 85#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 86#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 87#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 88 GENERATED_GBL_DATA_SIZE) 89#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 90 CONFIG_SYS_INIT_RAM_SIZE) 91 92/* 93 * environment organization 94 */ 95 96/* 97 * NAND driver 98 */ 99#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 100#define CONFIG_SYS_MAX_NAND_DEVICE 1 101#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 102#define CONFIG_MXC_NAND_HWECC 103#define CONFIG_SYS_NAND_LARGEPAGE 104 105/* NAND configuration for the NAND_SPL */ 106 107/* Start copying real U-Boot from the second page */ 108#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 109#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 110/* Load U-Boot to this address */ 111#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 112#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 113 114#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 115#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 116#define CONFIG_SYS_NAND_PAGE_COUNT 64 117#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 118#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 119 120/* Configuration of lowlevel_init.S (clocks and SDRAM) */ 121#define CCM_CCMR_SETUP 0x074B0BF5 122#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 123 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 124 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 125 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 126#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 127 PLL_MFN(12)) 128 129#define ESDMISC_MDDR_SETUP 0x00000004 130#define ESDMISC_MDDR_RESET_DL 0x0000000c 131#define ESDCFG0_MDDR_SETUP 0x006ac73a 132 133#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 134#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 135 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 136#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 137#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 138#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 139#define ESDCTL_RW ESDCTL_SETTINGS 140 141#endif /* __CONFIG_H */ 142