LXR uboot/include/configs/ti816x

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * ti816x_evm.h
   4 *
   5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   6 * Antoine Tenart, <atenart@adeneo-embedded.com>
   7 */
   8
   9#ifndef __CONFIG_TI816X_EVM_H
  10#define __CONFIG_TI816X_EVM_H
  11
  12#include <configs/ti_armv7_omap.h>
  13#include <asm/arch/omap.h>
  14
  15#define CONFIG_MACH_TYPE                MACH_TYPE_TI8168EVM
  16
  17#define CONFIG_EXTRA_ENV_SETTINGS       \
  18        DEFAULT_LINUX_BOOT_ENV \
  19        "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  20        "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  21
  22#define CONFIG_BOOTCOMMAND                      \
  23        "mmc rescan;"                           \
  24        "fatload mmc 0 ${loadaddr} uImage;"     \
  25        "bootm ${loadaddr}"                     \
  26
  27/* Clock Defines */
  28#define V_OSCK          24000000    /* Clock output from T2 */
  29#define V_SCLK          (V_OSCK >> 1)
  30
  31#define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2048MB */
  32#define CONFIG_SYS_SDRAM_BASE           0x80000000
  33
  34/**
  35 * Platform/Board specific defs
  36 */
  37#define CONFIG_SYS_CLK_FREQ     27000000
  38#define CONFIG_SYS_TIMERBASE    0x4802E000
  39#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
  40
  41/*
  42 * NS16550 Configuration
  43 */
  44#define CONFIG_SYS_NS16550_SERIAL
  45#define CONFIG_SYS_NS16550_REG_SIZE (-4)
  46#define CONFIG_SYS_NS16550_CLK      (48000000)
  47#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
  48
  49/* allow overwriting serial config and ethaddr */
  50#define CONFIG_ENV_OVERWRITE
  51
  52
  53/*
  54 * GPMC NAND block.  We support 1 device and the physical address to
  55 * access CS0 at is 0x8000000.
  56 */
  57#define CONFIG_SYS_NAND_BASE            0x8000000
  58#define CONFIG_SYS_MAX_NAND_DEVICE      1
  59
  60/* NAND: SPL related configs */
  61
  62/* NAND: device related configs */
  63#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  64#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  65                                         CONFIG_SYS_NAND_PAGE_SIZE)
  66#define CONFIG_SYS_NAND_PAGE_SIZE       2048
  67#define CONFIG_SYS_NAND_OOBSIZE         64
  68#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
  69/* NAND: driver related configs */
  70#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  71#define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
  72                                         10, 11, 12, 13, 14, 15, 16, 17, \
  73                                         18, 19, 20, 21, 22, 23, 24, 25, \
  74                                         26, 27, 28, 29, 30, 31, 32, 33, \
  75                                         34, 35, 36, 37, 38, 39, 40, 41, \
  76                                         42, 43, 44, 45, 46, 47, 48, 49, \
  77                                         50, 51, 52, 53, 54, 55, 56, 57, }
  78
  79#define CONFIG_SYS_NAND_ECCSIZE         512
  80#define CONFIG_SYS_NAND_ECCBYTES        14
  81#define CONFIG_SYS_NAND_ONFI_DETECTION
  82#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
  83#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x000c0000
  84#define CONFIG_SYS_ENV_SECT_SIZE        CONFIG_SYS_NAND_BLOCK_SIZE
  85
  86/* SPL */
  87/* Defines for SPL */
  88#define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
  89                                         CONFIG_SPL_TEXT_BASE)
  90
  91#define CONFIG_BOOTP_DNS2
  92#define CONFIG_BOOTP_SEND_HOSTNAME
  93#define CONFIG_NET_RETRY_COUNT  10
  94
  95/* Since SPL did pll and ddr initialization for us,
  96 * we don't need to do it twice.
  97 */
  98#ifndef CONFIG_SPL_BUILD
  99#define CONFIG_SKIP_LOWLEVEL_INIT
 100#endif
 101
 102/*
 103 * Disable MMC DM for SPL build and can be re-enabled after adding
 104 * DM support in SPL
 105 */
 106#ifdef CONFIG_SPL_BUILD
 107#undef CONFIG_DM_MMC
 108#undef CONFIG_TIMER
 109#endif
 110#endif
 111