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9#ifndef __LINUX_CLK_PROVIDER_H
10#define __LINUX_CLK_PROVIDER_H
11
12#include <dm.h>
13#include <linux/bitops.h>
14#include <linux/err.h>
15#include <clk-uclass.h>
16#include <linux/err.h>
17
18static inline void clk_dm(ulong id, struct clk *clk)
19{
20 if (!IS_ERR(clk))
21 clk->id = id;
22}
23
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30
31#define CLK_SET_RATE_GATE BIT(0)
32#define CLK_SET_PARENT_GATE BIT(1)
33#define CLK_SET_RATE_PARENT BIT(2)
34#define CLK_IGNORE_UNUSED BIT(3)
35
36#define CLK_IS_BASIC BIT(5)
37#define CLK_GET_RATE_NOCACHE BIT(6)
38#define CLK_SET_RATE_NO_REPARENT BIT(7)
39#define CLK_GET_ACCURACY_NOCACHE BIT(8)
40#define CLK_RECALC_NEW_RATES BIT(9)
41#define CLK_SET_RATE_UNGATE BIT(10)
42#define CLK_IS_CRITICAL BIT(11)
43
44#define CLK_OPS_PARENT_ENABLE BIT(12)
45
46#define CLK_DUTY_CYCLE_PARENT BIT(13)
47
48#define CLK_MUX_INDEX_ONE BIT(0)
49#define CLK_MUX_INDEX_BIT BIT(1)
50#define CLK_MUX_HIWORD_MASK BIT(2)
51#define CLK_MUX_READ_ONLY BIT(3)
52#define CLK_MUX_ROUND_CLOSEST BIT(4)
53
54struct clk_mux {
55 struct clk clk;
56 void __iomem *reg;
57 u32 *table;
58 u32 mask;
59 u8 shift;
60 u8 flags;
61
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64
65
66 const char * const *parent_names;
67 u8 num_parents;
68#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
69 u32 io_mux_val;
70#endif
71
72};
73
74#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
75extern const struct clk_ops clk_mux_ops;
76u8 clk_mux_get_parent(struct clk *clk);
77
78struct clk_gate {
79 struct clk clk;
80 void __iomem *reg;
81 u8 bit_idx;
82 u8 flags;
83#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
84 u32 io_gate_val;
85#endif
86};
87
88#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
89
90#define CLK_GATE_SET_TO_DISABLE BIT(0)
91#define CLK_GATE_HIWORD_MASK BIT(1)
92
93extern const struct clk_ops clk_gate_ops;
94struct clk *clk_register_gate(struct device *dev, const char *name,
95 const char *parent_name, unsigned long flags,
96 void __iomem *reg, u8 bit_idx,
97 u8 clk_gate_flags, spinlock_t *lock);
98
99struct clk_div_table {
100 unsigned int val;
101 unsigned int div;
102};
103
104struct clk_divider {
105 struct clk clk;
106 void __iomem *reg;
107 u8 shift;
108 u8 width;
109 u8 flags;
110 const struct clk_div_table *table;
111#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
112 u32 io_divider_val;
113#endif
114};
115
116#define clk_div_mask(width) ((1 << (width)) - 1)
117#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
118
119#define CLK_DIVIDER_ONE_BASED BIT(0)
120#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
121#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
122#define CLK_DIVIDER_HIWORD_MASK BIT(3)
123#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
124#define CLK_DIVIDER_READ_ONLY BIT(5)
125#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
126extern const struct clk_ops clk_divider_ops;
127unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
128 unsigned int val,
129 const struct clk_div_table *table,
130 unsigned long flags, unsigned long width);
131
132struct clk_fixed_factor {
133 struct clk clk;
134 unsigned int mult;
135 unsigned int div;
136};
137
138#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
139 clk)
140
141struct clk_fixed_rate {
142 struct clk clk;
143 unsigned long fixed_rate;
144};
145
146#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
147
148struct clk_composite {
149 struct clk clk;
150 struct clk_ops ops;
151
152 struct clk *mux;
153 struct clk *rate;
154 struct clk *gate;
155
156 const struct clk_ops *mux_ops;
157 const struct clk_ops *rate_ops;
158 const struct clk_ops *gate_ops;
159};
160
161#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
162
163struct clk *clk_register_composite(struct device *dev, const char *name,
164 const char * const *parent_names, int num_parents,
165 struct clk *mux_clk, const struct clk_ops *mux_ops,
166 struct clk *rate_clk, const struct clk_ops *rate_ops,
167 struct clk *gate_clk, const struct clk_ops *gate_ops,
168 unsigned long flags);
169
170int clk_register(struct clk *clk, const char *drv_name, const char *name,
171 const char *parent_name);
172
173struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
174 const char *parent_name, unsigned long flags,
175 unsigned int mult, unsigned int div);
176
177struct clk *clk_register_divider(struct device *dev, const char *name,
178 const char *parent_name, unsigned long flags,
179 void __iomem *reg, u8 shift, u8 width,
180 u8 clk_divider_flags);
181
182struct clk *clk_register_mux(struct device *dev, const char *name,
183 const char * const *parent_names, u8 num_parents,
184 unsigned long flags,
185 void __iomem *reg, u8 shift, u8 width,
186 u8 clk_mux_flags);
187
188const char *clk_hw_get_name(const struct clk *hw);
189ulong clk_generic_get_rate(struct clk *clk);
190
191static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
192{
193 return (struct clk *)dev_get_uclass_priv(dev);
194}
195#endif
196