LXR uboot/include/power/acpi

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright 2019 Google LLC
   4 */
   5
   6#ifndef __ACPI_PMC_H
   7#define __ACPI_PMC_H
   8
   9enum {
  10        GPE0_REG_MAX    = 4,
  11};
  12
  13/**
  14 * struct acpi_pmc_upriv - holds common data for the x86 PMC
  15 *
  16 * @pmc_bar0: Base address 0 of PMC
  17 * @pmc_bar1: Base address 2 of PMC
  18 * @acpi_base: Base address of ACPI block
  19 * @pm1_sts: PM1 status
  20 * @pm1_en: PM1 enable
  21 * @pm1_cnt: PM1 control
  22 * @gpe_cfg: Address of GPE_CFG register
  23 * @gpe0_dwx_mask: Mask to use for each GPE0 (typically 7 or 0xf)
  24 * @gpe0_dwx_shift_base: Base shift value to use for GPE0 (0 or 4)
  25 * @gpe0_sts_req: GPE0 status register offset
  26 * @gpe0_en_req: GPE0 enable register offset
  27 * @gpe0_sts: GPE0 status values
  28 * @gpe0_en: GPE0 enable values
  29 * @gpe0_dw: GPE0 DW values
  30 * @gpe0_count: Number of GPE0 registers
  31 * @tco1_sts: TCO1 status
  32 * @tco2_sts: TCO2 status
  33 * @prsts: Power and reset status
  34 * @gen_pmcon1: General power mgmt configuration 1
  35 * @gen_pmcon2: General power mgmt configuration 2
  36 * @gen_pmcon3: General power mgmt configuration 3
  37 */
  38struct acpi_pmc_upriv {
  39        void *pmc_bar0;
  40        void *pmc_bar2;
  41        u32 acpi_base;
  42        u16 pm1_sts;
  43        u16 pm1_en;
  44        u32 pm1_cnt;
  45        u32 *gpe_cfg;
  46        u32 gpe0_dwx_mask;
  47        u32 gpe0_dwx_shift_base;
  48        u32 gpe0_sts_reg;
  49        u32 gpe0_en_reg;
  50        u32 gpe0_sts[GPE0_REG_MAX];
  51        u32 gpe0_en[GPE0_REG_MAX];
  52        u32 gpe0_dw[GPE0_REG_MAX];
  53        int gpe0_count;
  54        u16 tco1_sts;
  55        u16 tco2_sts;
  56        u32 prsts;
  57        u32 gen_pmcon1;
  58        u32 gen_pmcon2;
  59        u32 gen_pmcon3;
  60};
  61
  62struct acpi_pmc_ops {
  63        /**
  64         * init() - Set up the PMC for use
  65         *
  66         * This reads the current state of the PMC. Most of the state is read
  67         * automatically by the uclass since it is common.
  68         *
  69         * This is optional.
  70         *
  71         * @dev: PMC device to use
  72         * @return 0 if OK, -ve on error
  73         */
  74        int (*init)(struct udevice *dev);
  75
  76        /**
  77         * prev_sleep_state() - Get the previous sleep state (optional)
  78         *
  79         * This reads various state registers and returns the sleep state from
  80         * which the system woke. If this method is not provided, the uclass
  81         * will return a calculated value.
  82         *
  83         * This is optional.
  84         *
  85         * @dev: PMC device to use
  86         * @prev_sleep_state: Previous sleep state as calculated by the uclass.
  87         *      The method can use this as the return value or calculate its
  88         *      own.
  89         *
  90         * @return enum acpi_sleep_state indicating the previous sleep state
  91         *      (ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error
  92         */
  93        int (*prev_sleep_state)(struct udevice *dev, int prev_sleep_state);
  94
  95        /**
  96         * disable_tco() - Disable the timer/counter
  97         *
  98         * Disables the timer/counter in the PMC
  99         *
 100         * This is optional.
 101         *
 102         * @dev: PMC device to use
 103         * @return 0
 104         */
 105        int (*disable_tco)(struct udevice *dev);
 106
 107        /**
 108         * global_reset_set_enable() - Enable/Disable global reset
 109         *
 110         * Enable or disable global reset. If global reset is enabled, both hard
 111         * reset and soft reset will trigger global reset, where both host and
 112         * TXE are reset. This is cleared on cold boot, hard reset, soft reset
 113         * and Sx.
 114         *
 115         * This is optional.
 116         *
 117         * @dev: PMC device to use
 118         * @enable: true to enable global reset, false to disable
 119         * @return 0
 120         */
 121        int (*global_reset_set_enable)(struct udevice *dev, bool enable);
 122};
 123
 124#define acpi_pmc_get_ops(dev)   ((struct acpi_pmc_ops *)(dev)->driver->ops)
 125
 126/**
 127 * init() - Set up the PMC for use
 128 *
 129 * This reads the current state of the PMC. This reads in the common registers,
 130 * then calls the device's init() method to read the SoC-specific registers.
 131 *
 132 * @return 0 if OK, -ve on error
 133 */
 134int pmc_init(struct udevice *dev);
 135
 136/**
 137 * pmc_prev_sleep_state() - Get the previous sleep state
 138 *
 139 * This reads various state registers and returns the sleep state from
 140 * which the system woke.
 141 *
 142 * @return enum acpi_sleep_state indicating the previous sleep state
 143 *      (ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error
 144 */
 145int pmc_prev_sleep_state(struct udevice *dev);
 146
 147/**
 148 * pmc_disable_tco() - Disable the timer/counter
 149 *
 150 * Disables the timer/counter in the PMC
 151 *
 152 * @dev: PMC device to use
 153 * @return 0
 154 */
 155int pmc_disable_tco(struct udevice *dev);
 156
 157/**
 158 * pmc_global_reset_set_enable() - Enable/Disable global reset
 159 *
 160 * Enable or disable global reset. If global reset is enabled, both hard
 161 * reset and soft reset will trigger global reset, where both host and
 162 * TXE are reset. This is cleared on cold boot, hard reset, soft reset
 163 * and Sx.
 164 *
 165 * @dev: PMC device to use
 166 * @enable: true to enable global reset, false to disable
 167 * @return 0
 168 */
 169int pmc_global_reset_set_enable(struct udevice *dev, bool enable);
 170
 171int pmc_ofdata_to_uc_platdata(struct udevice *dev);
 172
 173int pmc_disable_tco_base(ulong tco_base);
 174
 175void pmc_dump_info(struct udevice *dev);
 176
 177/**
 178 * pmc_gpe_init() - Set up general-purpose events
 179 *
 180 * @dev: PMC device
 181 * @return 0 if OK, -ve on error
 182 */
 183int pmc_gpe_init(struct udevice *dev);
 184
 185#endif
 186