LXR uboot/arch/arm/include/asm/omap

   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 * Syed Mohammed Khasim <khasim@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation's version 2 of
  12 * the License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#ifndef OMAP_MMC_H_
  26#define OMAP_MMC_H_
  27
  28#include <mmc.h>
  29#ifndef __ASSEMBLY__
  30#include <linux/bitops.h>
  31#endif
  32
  33struct hsmmc {
  34#ifndef CONFIG_OMAP34XX
  35        unsigned int hl_rev;
  36        unsigned int hl_hwinfo;
  37        unsigned int hl_sysconfig;
  38        unsigned char res0[0xf4];
  39#endif
  40        unsigned char res1[0x10];
  41        unsigned int sysconfig;         /* 0x10 */
  42        unsigned int sysstatus;         /* 0x14 */
  43        unsigned char res2[0x14];
  44        unsigned int con;               /* 0x2C */
  45        unsigned int pwcnt;             /* 0x30 */
  46        unsigned int dll;               /* 0x34 */
  47        unsigned char res3[0xcc];
  48        unsigned int blk;               /* 0x104 */
  49        unsigned int arg;               /* 0x108 */
  50        unsigned int cmd;               /* 0x10C */
  51        unsigned int rsp10;             /* 0x110 */
  52        unsigned int rsp32;             /* 0x114 */
  53        unsigned int rsp54;             /* 0x118 */
  54        unsigned int rsp76;             /* 0x11C */
  55        unsigned int data;              /* 0x120 */
  56        unsigned int pstate;            /* 0x124 */
  57        unsigned int hctl;              /* 0x128 */
  58        unsigned int sysctl;            /* 0x12C */
  59        unsigned int stat;              /* 0x130 */
  60        unsigned int ie;                /* 0x134 */
  61        unsigned char res4[0x4];
  62        unsigned int ac12;              /* 0x13C */
  63        unsigned int capa;              /* 0x140 */
  64        unsigned int capa2;             /* 0x144 */
  65        unsigned char res5[0xc];
  66        unsigned int admaes;            /* 0x154 */
  67        unsigned int admasal;           /* 0x158 */
  68};
  69
  70struct omap_hsmmc_plat {
  71        struct mmc_config cfg;
  72        struct hsmmc *base_addr;
  73        struct mmc *mmc;
  74        u32 controller_flags;
  75        const char *hw_rev;
  76};
  77
  78/*
  79 * OMAP HS MMC Bit definitions
  80 */
  81#define MADMA_EN                        (0x1 << 0)
  82#define MMC_SOFTRESET                   (0x1 << 1)
  83#define RESETDONE                       (0x1 << 0)
  84#define NOOPENDRAIN                     (0x0 << 0)
  85#define OPENDRAIN                       (0x1 << 0)
  86#define OD                              (0x1 << 0)
  87#define INIT_NOINIT                     (0x0 << 1)
  88#define INIT_INITSTREAM                 (0x1 << 1)
  89#define HR_NOHOSTRESP                   (0x0 << 2)
  90#define STR_BLOCK                       (0x0 << 3)
  91#define MODE_FUNC                       (0x0 << 4)
  92#define DW8_1_4BITMODE                  (0x0 << 5)
  93#define MIT_CTO                         (0x0 << 6)
  94#define CDP_ACTIVEHIGH                  (0x0 << 7)
  95#define WPP_ACTIVEHIGH                  (0x0 << 8)
  96#define RESERVED_MASK                   (0x3 << 9)
  97#define CTPL_MMC_SD                     (0x0 << 11)
  98#define DDR                             (0x1 << 19)
  99#define DMA_MASTER                      (0x1 << 20)
 100#define BLEN_512BYTESLEN                (0x200 << 0)
 101#define NBLK_STPCNT                     (0x0 << 16)
 102#define DE_ENABLE                       (0x1 << 0)
 103#define BCE_ENABLE                      (0x1 << 1)
 104#define ACEN_ENABLE                     (0x1 << 2)
 105#define DDIR_OFFSET                     (4)
 106#define DDIR_MASK                       (0x1 << 4)
 107#define DDIR_WRITE                      (0x0 << 4)
 108#define DDIR_READ                       (0x1 << 4)
 109#define MSBS_SGLEBLK                    (0x0 << 5)
 110#define MSBS_MULTIBLK                   (0x1 << 5)
 111#define RSP_TYPE_OFFSET                 (16)
 112#define RSP_TYPE_MASK                   (0x3 << 16)
 113#define RSP_TYPE_NORSP                  (0x0 << 16)
 114#define RSP_TYPE_LGHT136                (0x1 << 16)
 115#define RSP_TYPE_LGHT48                 (0x2 << 16)
 116#define RSP_TYPE_LGHT48B                (0x3 << 16)
 117#define CCCE_NOCHECK                    (0x0 << 19)
 118#define CCCE_CHECK                      (0x1 << 19)
 119#define CICE_NOCHECK                    (0x0 << 20)
 120#define CICE_CHECK                      (0x1 << 20)
 121#define DP_OFFSET                       (21)
 122#define DP_MASK                         (0x1 << 21)
 123#define DP_NO_DATA                      (0x0 << 21)
 124#define DP_DATA                         (0x1 << 21)
 125#define CMD_TYPE_NORMAL                 (0x0 << 22)
 126#define INDEX_OFFSET                    (24)
 127#define INDEX_MASK                      (0x3f << 24)
 128#define INDEX(i)                        (i << 24)
 129#define DATI_MASK                       (0x1 << 1)
 130#define CMDI_MASK                       (0x1 << 0)
 131#define DTW_1_BITMODE                   (0x0 << 1)
 132#define DTW_4_BITMODE                   (0x1 << 1)
 133#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 134#define SDBP_PWROFF                     (0x0 << 8)
 135#define SDBP_PWRON                      (0x1 << 8)
 136#define SDVS_MASK                       (0x7 << 9)
 137#define SDVS_1V8                        (0x5 << 9)
 138#define SDVS_3V0                        (0x6 << 9)
 139#define SDVS_3V3                        (0x7 << 9)
 140#define DMA_SELECT                      (0x2 << 3)
 141#define ICE_MASK                        (0x1 << 0)
 142#define ICE_STOP                        (0x0 << 0)
 143#define ICS_MASK                        (0x1 << 1)
 144#define ICS_NOTREADY                    (0x0 << 1)
 145#define ICE_OSCILLATE                   (0x1 << 0)
 146#define CEN_MASK                        (0x1 << 2)
 147#define CEN_ENABLE                      (0x1 << 2)
 148#define CLKD_OFFSET                     (6)
 149#define CLKD_MASK                       (0x3FF << 6)
 150#define DTO_MASK                        (0xF << 16)
 151#define DTO_15THDTO                     (0xE << 16)
 152#define SOFTRESETALL                    (0x1 << 24)
 153#define CC_MASK                         (0x1 << 0)
 154#define TC_MASK                         (0x1 << 1)
 155#define BWR_MASK                        (0x1 << 4)
 156#define BRR_MASK                        (0x1 << 5)
 157#define ERRI_MASK                       (0x1 << 15)
 158#define IE_CC                           (0x01 << 0)
 159#define IE_TC                           (0x01 << 1)
 160#define IE_BWR                          (0x01 << 4)
 161#define IE_BRR                          (0x01 << 5)
 162#define IE_CTO                          (0x01 << 16)
 163#define IE_CCRC                         (0x01 << 17)
 164#define IE_CEB                          (0x01 << 18)
 165#define IE_CIE                          (0x01 << 19)
 166#define IE_DTO                          (0x01 << 20)
 167#define IE_DCRC                         (0x01 << 21)
 168#define IE_DEB                          (0x01 << 22)
 169#define IE_ADMAE                        (0x01 << 25)
 170#define IE_CERR                         (0x01 << 28)
 171#define IE_BADA                         (0x01 << 29)
 172
 173#define VS33_3V3SUP                     BIT(24)
 174#define VS30_3V0SUP                     BIT(25)
 175#define VS18_1V8SUP                     BIT(26)
 176
 177#define AC12_ET                         BIT(22)
 178#define AC12_V1V8_SIGEN                 BIT(19)
 179#define AC12_SCLK_SEL                   BIT(23)
 180#define AC12_UHSMC_MASK                 (7 << 16)
 181#define AC12_UHSMC_DDR50                (4 << 16)
 182#define AC12_UHSMC_SDR104               (3 << 16)
 183#define AC12_UHSMC_SDR50                (2 << 16)
 184#define AC12_UHSMC_SDR25                (1 << 16)
 185#define AC12_UHSMC_SDR12                (0 << 16)
 186#define AC12_UHSMC_RES                  (0x7 << 16)
 187
 188/* Driver definitions */
 189#define MMCSD_SECTOR_SIZE               512
 190#define MMC_CARD                        0
 191#define SD_CARD                         1
 192#define BYTE_MODE                       0
 193#define SECTOR_MODE                     1
 194#define CLK_INITSEQ                     0
 195#define CLK_400KHZ                      1
 196#define CLK_MISC                        2
 197
 198#define CLKD_MAX                        0x3FF   /* max clock divisor: 1023 */
 199
 200#define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 201#define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 202
 203/* Clock Configurations and Macros */
 204#ifdef CONFIG_OMAP54XX
 205#define MMC_CLOCK_REFERENCE     192 /* MHz */
 206#else
 207#define MMC_CLOCK_REFERENCE     96 /* MHz */
 208#endif
 209
 210/* DLL */
 211#define DLL_SWT                 BIT(20)
 212#define DLL_FORCE_SR_C_SHIFT    13
 213#define DLL_FORCE_SR_C_MASK     0x7f
 214#define DLL_FORCE_VALUE         BIT(12)
 215#define DLL_CALIB               BIT(1)
 216
 217#define MAX_PHASE_DELAY         0x7c
 218
 219/* CAPA2 */
 220#define CAPA2_TSDR50            BIT(13)
 221
 222#define mmc_reg_out(addr, mask, val)\
 223        writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 224
 225#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
 226                IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
 227                IE_BRR | IE_BWR | IE_TC | IE_CC)
 228
 229#define CON_CLKEXTFREE          BIT(16)
 230#define CON_PADEN               BIT(15)
 231#define PSTATE_CLEV             BIT(24)
 232#define PSTATE_DLEV             (0xF << 20)
 233#define PSTATE_DLEV_DAT0        (0x1 << 20)
 234
 235int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 236                int wp_gpio);
 237
 238void vmmc_pbias_config(uint voltage);
 239void board_mmc_poweron_ldo(uint voltage);
 240#endif /* OMAP_MMC_H_ */
 241