LXR uboot/arch/arm/mach-davinci/timer.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2003
   4 * Texas Instruments <www.ti.com>
   5 *
   6 * (C) Copyright 2002
   7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8 * Marius Groeger <mgroeger@sysgo.de>
   9 *
  10 * (C) Copyright 2002
  11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12 * Alex Zuepke <azu@sysgo.de>
  13 *
  14 * (C) Copyright 2002-2004
  15 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16 *
  17 * (C) Copyright 2004
  18 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  19 *
  20 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  21 */
  22
  23#include <common.h>
  24#include <init.h>
  25#include <time.h>
  26#include <asm/io.h>
  27#include <asm/arch/timer_defs.h>
  28#include <div64.h>
  29#include <linux/delay.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33static struct davinci_timer * const timer =
  34        (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
  35
  36#define TIMER_LOAD_VAL  0xffffffff
  37
  38#define TIM_CLK_DIV     16
  39
  40int timer_init(void)
  41{
  42        /* We are using timer34 in unchained 32-bit mode, full speed */
  43        writel(0x0, &timer->tcr);
  44        writel(0x0, &timer->tgcr);
  45        writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
  46        writel(0x0, &timer->tim34);
  47        writel(TIMER_LOAD_VAL, &timer->prd34);
  48        writel(2 << 22, &timer->tcr);
  49        gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
  50        gd->arch.timer_reset_value = 0;
  51
  52        return(0);
  53}
  54
  55/*
  56 * Get the current 64 bit timer tick count
  57 */
  58unsigned long long get_ticks(void)
  59{
  60        unsigned long now = readl(&timer->tim34);
  61
  62        /* increment tbu if tbl has rolled over */
  63        if (now < gd->arch.tbl)
  64                gd->arch.tbu++;
  65        gd->arch.tbl = now;
  66
  67        return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  68}
  69
  70ulong get_timer(ulong base)
  71{
  72        unsigned long long timer_diff;
  73
  74        timer_diff = get_ticks() - gd->arch.timer_reset_value;
  75
  76        return lldiv(timer_diff,
  77                     (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
  78}
  79
  80void __udelay(unsigned long usec)
  81{
  82        unsigned long long endtime;
  83
  84        endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
  85                        1000000UL);
  86        endtime += get_ticks();
  87
  88        while (get_ticks() < endtime)
  89                ;
  90}
  91
  92/*
  93 * This function is derived from PowerPC code (timebase clock frequency).
  94 * On ARM it returns the number of timer ticks per second.
  95 */
  96ulong get_tbclk(void)
  97{
  98        return gd->arch.timer_rate_hz;
  99}
 100
 101#ifdef CONFIG_HW_WATCHDOG
 102static struct davinci_timer * const wdttimer =
 103        (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
 104
 105/*
 106 * See prufw2.pdf for using Timer as a WDT
 107 */
 108void davinci_hw_watchdog_enable(void)
 109{
 110        writel(0x0, &wdttimer->tcr);
 111        writel(0x0, &wdttimer->tgcr);
 112        /* TIMMODE = 2h */
 113        writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
 114        writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
 115        writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
 116        writel(2 << 22, &wdttimer->tcr);
 117        writel(0x0, &wdttimer->tim12);
 118        writel(0x0, &wdttimer->tim34);
 119        /* set WDEN bit, WDKEY 0xa5c6 */
 120        writel(0xa5c64000, &wdttimer->wdtcr);
 121        /* clear counter register */
 122        writel(0xda7e4000, &wdttimer->wdtcr);
 123}
 124
 125void davinci_hw_watchdog_reset(void)
 126{
 127        writel(0xa5c64000, &wdttimer->wdtcr);
 128        writel(0xda7e4000, &wdttimer->wdtcr);
 129}
 130#endif
 131