1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 - 2018 Xilinx, Inc. 4 */ 5 6#ifndef __ASSEMBLY__ 7#include <linux/bitops.h> 8#endif 9 10#define VERSAL_CRL_APB_BASEADDR 0xFF5E0000 11 12#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) 13 14#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) 15#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 16 17struct crlapb_regs { 18 u32 reserved0[67]; 19 u32 cpu_r5_ctrl; 20 u32 reserved; 21 u32 iou_switch_ctrl; /* 0x114 */ 22 u32 reserved1[13]; 23 u32 timestamp_ref_ctrl; /* 0x14c */ 24 u32 reserved3[108]; 25 u32 rst_cpu_r5; 26 u32 reserved2[17]; 27 u32 rst_timestamp; /* 0x348 */ 28}; 29 30#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) 31 32#define VERSAL_IOU_SCNTR_SECURE 0xFF140000 33 34#define IOU_SCNTRS_CONTROL_EN 1 35 36struct iou_scntrs_regs { 37 u32 counter_control_register; /* 0x0 */ 38 u32 reserved0[7]; 39 u32 base_frequency_id_register; /* 0x20 */ 40}; 41 42#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE) 43 44#define VERSAL_TCM_BASE_ADDR 0xFFE00000 45#define VERSAL_TCM_SIZE 0x40000 46 47#define VERSAL_RPU_BASEADDR 0xFF9A0000 48 49struct rpu_regs { 50 u32 rpu_glbl_ctrl; 51 u32 reserved0[63]; 52 u32 rpu0_cfg; /* 0x100 */ 53 u32 reserved1[63]; 54 u32 rpu1_cfg; /* 0x200 */ 55}; 56 57#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) 58 59#define VERSAL_CRP_BASEADDR 0xF1260000 60 61struct crp_regs { 62 u32 reserved0[128]; 63 u32 boot_mode_usr; 64}; 65 66#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR) 67 68/* Bootmode setting values */ 69#define BOOT_MODES_MASK 0x0000000F 70#define QSPI_MODE_24BIT 0x00000001 71#define QSPI_MODE_32BIT 0x00000002 72#define SD_MODE 0x00000003 /* sd 0 */ 73#define SD_MODE1 0x00000005 /* sd 1 */ 74#define EMMC_MODE 0x00000006 75#define USB_MODE 0x00000007 76#define OSPI_MODE 0x00000008 77#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 78#define JTAG_MODE 0x00000000 79#define BOOT_MODE_USE_ALT 0x100 80#define BOOT_MODE_ALT_SHIFT 12 81