LXR uboot/arch/x86/cpu/broadwell/cpu

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2016 Google, Inc
   4 *
   5 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <cpu.h>
  11#include <init.h>
  12#include <log.h>
  13#include <asm/cpu.h>
  14#include <asm/cpu_x86.h>
  15#include <asm/cpu_common.h>
  16#include <asm/intel_regs.h>
  17#include <asm/msr.h>
  18#include <asm/post.h>
  19#include <asm/turbo.h>
  20#include <asm/arch/cpu.h>
  21#include <asm/arch/pch.h>
  22#include <asm/arch/rcb.h>
  23#include <linux/delay.h>
  24
  25struct cpu_broadwell_priv {
  26        bool ht_disabled;
  27};
  28
  29/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  30static const u8 power_limit_time_sec_to_msr[] = {
  31        [0]   = 0x00,
  32        [1]   = 0x0a,
  33        [2]   = 0x0b,
  34        [3]   = 0x4b,
  35        [4]   = 0x0c,
  36        [5]   = 0x2c,
  37        [6]   = 0x4c,
  38        [7]   = 0x6c,
  39        [8]   = 0x0d,
  40        [10]  = 0x2d,
  41        [12]  = 0x4d,
  42        [14]  = 0x6d,
  43        [16]  = 0x0e,
  44        [20]  = 0x2e,
  45        [24]  = 0x4e,
  46        [28]  = 0x6e,
  47        [32]  = 0x0f,
  48        [40]  = 0x2f,
  49        [48]  = 0x4f,
  50        [56]  = 0x6f,
  51        [64]  = 0x10,
  52        [80]  = 0x30,
  53        [96]  = 0x50,
  54        [112] = 0x70,
  55        [128] = 0x11,
  56};
  57
  58/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  59static const u8 power_limit_time_msr_to_sec[] = {
  60        [0x00] = 0,
  61        [0x0a] = 1,
  62        [0x0b] = 2,
  63        [0x4b] = 3,
  64        [0x0c] = 4,
  65        [0x2c] = 5,
  66        [0x4c] = 6,
  67        [0x6c] = 7,
  68        [0x0d] = 8,
  69        [0x2d] = 10,
  70        [0x4d] = 12,
  71        [0x6d] = 14,
  72        [0x0e] = 16,
  73        [0x2e] = 20,
  74        [0x4e] = 24,
  75        [0x6e] = 28,
  76        [0x0f] = 32,
  77        [0x2f] = 40,
  78        [0x4f] = 48,
  79        [0x6f] = 56,
  80        [0x10] = 64,
  81        [0x30] = 80,
  82        [0x50] = 96,
  83        [0x70] = 112,
  84        [0x11] = 128,
  85};
  86
  87#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  88int arch_cpu_init(void)
  89{
  90        return 0;
  91}
  92#endif
  93
  94/*
  95 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
  96 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
  97 * when a core is woken up
  98 */
  99static int pcode_ready(void)
 100{
 101        int wait_count;
 102        const int delay_step = 10;
 103
 104        wait_count = 0;
 105        do {
 106                if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
 107                                MAILBOX_RUN_BUSY))
 108                        return 0;
 109                wait_count += delay_step;
 110                udelay(delay_step);
 111        } while (wait_count < 1000);
 112
 113        return -ETIMEDOUT;
 114}
 115
 116static u32 pcode_mailbox_read(u32 command)
 117{
 118        int ret;
 119
 120        ret = pcode_ready();
 121        if (ret) {
 122                debug("PCODE: mailbox timeout on wait ready\n");
 123                return ret;
 124        }
 125
 126        /* Send command and start transaction */
 127        writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 128
 129        ret = pcode_ready();
 130        if (ret) {
 131                debug("PCODE: mailbox timeout on completion\n");
 132                return ret;
 133        }
 134
 135        /* Read mailbox */
 136        return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
 137}
 138
 139static int pcode_mailbox_write(u32 command, u32 data)
 140{
 141        int ret;
 142
 143        ret = pcode_ready();
 144        if (ret) {
 145                debug("PCODE: mailbox timeout on wait ready\n");
 146                return ret;
 147        }
 148
 149        writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
 150
 151        /* Send command and start transaction */
 152        writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 153
 154        ret = pcode_ready();
 155        if (ret) {
 156                debug("PCODE: mailbox timeout on completion\n");
 157                return ret;
 158        }
 159
 160        return 0;
 161}
 162
 163/* @dev is the CPU device */
 164static void initialize_vr_config(struct udevice *dev)
 165{
 166        int ramp, min_vid;
 167        msr_t msr;
 168
 169        debug("Initializing VR config\n");
 170
 171        /* Configure VR_CURRENT_CONFIG */
 172        msr = msr_read(MSR_VR_CURRENT_CONFIG);
 173        /*
 174         * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
 175         * on ULT systems
 176         */
 177        msr.hi &= 0xc0000000;
 178        msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */
 179        msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */
 180        msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
 181        msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
 182        /* Leave the max instantaneous current limit (12:0) to default */
 183        msr_write(MSR_VR_CURRENT_CONFIG, msr);
 184
 185        /* Configure VR_MISC_CONFIG MSR */
 186        msr = msr_read(MSR_VR_MISC_CONFIG);
 187        /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
 188        msr.hi &= ~(0x3ff << (40 - 32));
 189        msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
 190        /* Set IOUT_OFFSET to 0 */
 191        msr.hi &= ~0xff;
 192        /* Set entry ramp rate to slow */
 193        msr.hi &= ~(1 << (51 - 32));
 194        /* Enable decay mode on C-state entry */
 195        msr.hi |= (1 << (52 - 32));
 196        /* Set the slow ramp rate */
 197        msr.hi &= ~(0x3 << (53 - 32));
 198        /* Configure the C-state exit ramp rate */
 199        ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 200                              "intel,slow-ramp", -1);
 201        if (ramp != -1) {
 202                /* Configured slow ramp rate */
 203                msr.hi |= ((ramp & 0x3) << (53 - 32));
 204                /* Set exit ramp rate to slow */
 205                msr.hi &= ~(1 << (50 - 32));
 206        } else {
 207                /* Fast ramp rate / 4 */
 208                msr.hi |= (0x01 << (53 - 32));
 209                /* Set exit ramp rate to fast */
 210                msr.hi |= (1 << (50 - 32));
 211        }
 212        /* Set MIN_VID (31:24) to allow CPU to have full control */
 213        msr.lo &= ~0xff000000;
 214        min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 215                                 "intel,min-vid", 0);
 216        msr.lo |= (min_vid & 0xff) << 24;
 217        msr_write(MSR_VR_MISC_CONFIG, msr);
 218
 219        /*  Configure VR_MISC_CONFIG2 MSR */
 220        msr = msr_read(MSR_VR_MISC_CONFIG2);
 221        msr.lo &= ~0xffff;
 222        /*
 223         * Allow CPU to control minimum voltage completely (15:8) and
 224         * set the fast ramp voltage in 10mV steps
 225         */
 226        if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
 227                msr.lo |= 0x006a; /* 1.56V */
 228        else
 229                msr.lo |= 0x006f; /* 1.60V */
 230        msr_write(MSR_VR_MISC_CONFIG2, msr);
 231
 232        /* Set C9/C10 VCC Min */
 233        pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
 234}
 235
 236static int calibrate_24mhz_bclk(void)
 237{
 238        int err_code;
 239        int ret;
 240
 241        ret = pcode_ready();
 242        if (ret)
 243                return ret;
 244
 245        /* A non-zero value initiates the PCODE calibration */
 246        writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
 247        writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
 248               MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 249
 250        ret = pcode_ready();
 251        if (ret)
 252                return ret;
 253
 254        err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
 255
 256        debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
 257
 258        /* Read the calibrated value */
 259        writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
 260               MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 261
 262        ret = pcode_ready();
 263        if (ret)
 264                return ret;
 265
 266        debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
 267              readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
 268
 269        return 0;
 270}
 271
 272static void configure_pch_power_sharing(void)
 273{
 274        u32 pch_power, pch_power_ext, pmsync, pmsync2;
 275        int i;
 276
 277        /* Read PCH Power levels from PCODE */
 278        pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
 279        pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
 280
 281        debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
 282              pch_power_ext);
 283
 284        pmsync = readl(RCB_REG(PMSYNC_CONFIG));
 285        pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
 286
 287        /*
 288         * Program PMSYNC_TPR_CONFIG PCH power limit values
 289         *  pmsync[0:4]   = mailbox[0:5]
 290         *  pmsync[8:12]  = mailbox[6:11]
 291         *  pmsync[16:20] = mailbox[12:17]
 292         */
 293        for (i = 0; i < 3; i++) {
 294                u32 level = pch_power & 0x3f;
 295
 296                pch_power >>= 6;
 297                pmsync &= ~(0x1f << (i * 8));
 298                pmsync |= (level & 0x1f) << (i * 8);
 299        }
 300        writel(pmsync, RCB_REG(PMSYNC_CONFIG));
 301
 302        /*
 303         * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
 304         *  pmsync2[0:4]   = mailbox[23:18]
 305         *  pmsync2[8:12]  = mailbox_ext[6:11]
 306         *  pmsync2[16:20] = mailbox_ext[12:17]
 307         *  pmsync2[24:28] = mailbox_ext[18:22]
 308         */
 309        pmsync2 &= ~0x1f;
 310        pmsync2 |= pch_power & 0x1f;
 311
 312        for (i = 1; i < 4; i++) {
 313                u32 level = pch_power_ext & 0x3f;
 314
 315                pch_power_ext >>= 6;
 316                pmsync2 &= ~(0x1f << (i * 8));
 317                pmsync2 |= (level & 0x1f) << (i * 8);
 318        }
 319        writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
 320}
 321
 322static int bsp_init_before_ap_bringup(struct udevice *dev)
 323{
 324        int ret;
 325
 326        initialize_vr_config(dev);
 327        ret = calibrate_24mhz_bclk();
 328        if (ret)
 329                return ret;
 330        configure_pch_power_sharing();
 331
 332        return 0;
 333}
 334
 335static void set_max_ratio(void)
 336{
 337        msr_t msr, perf_ctl;
 338
 339        perf_ctl.hi = 0;
 340
 341        /* Check for configurable TDP option */
 342        if (turbo_get_state() == TURBO_ENABLED) {
 343                msr = msr_read(MSR_TURBO_RATIO_LIMIT);
 344                perf_ctl.lo = (msr.lo & 0xff) << 8;
 345        } else if (cpu_config_tdp_levels()) {
 346                /* Set to nominal TDP ratio */
 347                msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
 348                perf_ctl.lo = (msr.lo & 0xff) << 8;
 349        } else {
 350                /* Platform Info bits 15:8 give max ratio */
 351                msr = msr_read(MSR_PLATFORM_INFO);
 352                perf_ctl.lo = msr.lo & 0xff00;
 353        }
 354        msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 355
 356        debug("cpu: frequency set to %d\n",
 357              ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
 358}
 359
 360int broadwell_init(struct udevice *dev)
 361{
 362        struct cpu_broadwell_priv *priv = dev_get_priv(dev);
 363        int num_threads;
 364        int num_cores;
 365        msr_t msr;
 366        int ret;
 367
 368        msr = msr_read(CORE_THREAD_COUNT_MSR);
 369        num_threads = (msr.lo >> 0) & 0xffff;
 370        num_cores = (msr.lo >> 16) & 0xffff;
 371        debug("CPU has %u cores, %u threads enabled\n", num_cores,
 372              num_threads);
 373
 374        priv->ht_disabled = num_threads == num_cores;
 375
 376        ret = bsp_init_before_ap_bringup(dev);
 377        if (ret)
 378                return ret;
 379
 380        set_max_ratio();
 381
 382        return ret;
 383}
 384
 385static void configure_mca(void)
 386{
 387        msr_t msr;
 388        const unsigned int mcg_cap_msr = 0x179;
 389        int i;
 390        int num_banks;
 391
 392        msr = msr_read(mcg_cap_msr);
 393        num_banks = msr.lo & 0xff;
 394        msr.lo = 0;
 395        msr.hi = 0;
 396        /*
 397         * TODO(adurbin): This should only be done on a cold boot. Also, some
 398         * of these banks are core vs package scope. For now every CPU clears
 399         * every bank
 400         */
 401        for (i = 0; i < num_banks; i++)
 402                msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
 403}
 404
 405static void enable_lapic_tpr(void)
 406{
 407        msr_t msr;
 408
 409        msr = msr_read(MSR_PIC_MSG_CONTROL);
 410        msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
 411        msr_write(MSR_PIC_MSG_CONTROL, msr);
 412}
 413
 414static void configure_c_states(void)
 415{
 416        msr_t msr;
 417
 418        msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
 419        msr.lo |= (1 << 31);    /* Timed MWAIT Enable */
 420        msr.lo |= (1 << 30);    /* Package c-state Undemotion Enable */
 421        msr.lo |= (1 << 29);    /* Package c-state Demotion Enable */
 422        msr.lo |= (1 << 28);    /* C1 Auto Undemotion Enable */
 423        msr.lo |= (1 << 27);    /* C3 Auto Undemotion Enable */
 424        msr.lo |= (1 << 26);    /* C1 Auto Demotion Enable */
 425        msr.lo |= (1 << 25);    /* C3 Auto Demotion Enable */
 426        msr.lo &= ~(1 << 10);   /* Disable IO MWAIT redirection */
 427        /* The deepest package c-state defaults to factory-configured value */
 428        msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
 429
 430        msr = msr_read(MSR_MISC_PWR_MGMT);
 431        msr.lo &= ~(1 << 0);    /* Enable P-state HW_ALL coordination */
 432        msr_write(MSR_MISC_PWR_MGMT, msr);
 433
 434        msr = msr_read(MSR_POWER_CTL);
 435        msr.lo |= (1 << 18);    /* Enable Energy Perf Bias MSR 0x1b0 */
 436        msr.lo |= (1 << 1);     /* C1E Enable */
 437        msr.lo |= (1 << 0);     /* Bi-directional PROCHOT# */
 438        msr_write(MSR_POWER_CTL, msr);
 439
 440        /* C-state Interrupt Response Latency Control 0 - package C3 latency */
 441        msr.hi = 0;
 442        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
 443        msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
 444
 445        /* C-state Interrupt Response Latency Control 1 */
 446        msr.hi = 0;
 447        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
 448        msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
 449
 450        /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
 451        msr.hi = 0;
 452        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 453        msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 454
 455        /* C-state Interrupt Response Latency Control 3 - package C8 */
 456        msr.hi = 0;
 457        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
 458        msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 459
 460        /* C-state Interrupt Response Latency Control 4 - package C9 */
 461        msr.hi = 0;
 462        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
 463        msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 464
 465        /* C-state Interrupt Response Latency Control 5 - package C10 */
 466        msr.hi = 0;
 467        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
 468        msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 469}
 470
 471static void configure_misc(void)
 472{
 473        msr_t msr;
 474
 475        msr = msr_read(MSR_IA32_MISC_ENABLE);
 476        msr.lo |= MISC_ENABLE_FAST_STRING;
 477        msr.lo |= MISC_ENABLE_TM1;
 478        msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
 479        msr_write(MSR_IA32_MISC_ENABLE, msr);
 480
 481        /* Disable thermal interrupts */
 482        msr.lo = 0;
 483        msr.hi = 0;
 484        msr_write(MSR_IA32_THERM_INTERRUPT, msr);
 485
 486        /* Enable package critical interrupt only */
 487        msr.lo = 1 << 4;
 488        msr.hi = 0;
 489        msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
 490}
 491
 492static void configure_dca_cap(void)
 493{
 494        struct cpuid_result cpuid_regs;
 495        msr_t msr;
 496
 497        /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
 498        cpuid_regs = cpuid(1);
 499        if (cpuid_regs.ecx & (1 << 18)) {
 500                msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
 501                msr.lo |= 1;
 502                msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
 503        }
 504}
 505
 506static void set_energy_perf_bias(u8 policy)
 507{
 508        msr_t msr;
 509        int ecx;
 510
 511        /* Determine if energy efficient policy is supported */
 512        ecx = cpuid_ecx(0x6);
 513        if (!(ecx & (1 << 3)))
 514                return;
 515
 516        /* Energy Policy is bits 3:0 */
 517        msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
 518        msr.lo &= ~0xf;
 519        msr.lo |= policy & 0xf;
 520        msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
 521
 522        debug("cpu: energy policy set to %u\n", policy);
 523}
 524
 525/* All CPUs including BSP will run the following function */
 526static void cpu_core_init(struct udevice *dev)
 527{
 528        /* Clear out pending MCEs */
 529        configure_mca();
 530
 531        /* Enable the local cpu apics */
 532        enable_lapic_tpr();
 533
 534        /* Configure C States */
 535        configure_c_states();
 536
 537        /* Configure Enhanced SpeedStep and Thermal Sensors */
 538        configure_misc();
 539
 540        /* Thermal throttle activation offset */
 541        cpu_configure_thermal_target(dev);
 542
 543        /* Enable Direct Cache Access */
 544        configure_dca_cap();
 545
 546        /* Set energy policy */
 547        set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 548
 549        /* Enable Turbo */
 550        turbo_enable();
 551}
 552
 553/*
 554 * Configure processor power limits if possible
 555 * This must be done AFTER set of BIOS_RESET_CPL
 556 */
 557void cpu_set_power_limits(int power_limit_1_time)
 558{
 559        msr_t msr;
 560        msr_t limit;
 561        uint power_unit;
 562        uint tdp, min_power, max_power, max_time;
 563        u8 power_limit_1_val;
 564
 565        msr = msr_read(MSR_PLATFORM_INFO);
 566        if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
 567                power_limit_1_time = 28;
 568
 569        if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 570                return;
 571
 572        /* Get units */
 573        msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
 574        power_unit = 2 << ((msr.lo & 0xf) - 1);
 575
 576        /* Get power defaults for this SKU */
 577        msr = msr_read(MSR_PKG_POWER_SKU);
 578        tdp = msr.lo & 0x7fff;
 579        min_power = (msr.lo >> 16) & 0x7fff;
 580        max_power = msr.hi & 0x7fff;
 581        max_time = (msr.hi >> 16) & 0x7f;
 582
 583        debug("CPU TDP: %u Watts\n", tdp / power_unit);
 584
 585        if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
 586                power_limit_1_time = power_limit_time_msr_to_sec[max_time];
 587
 588        if (min_power > 0 && tdp < min_power)
 589                tdp = min_power;
 590
 591        if (max_power > 0 && tdp > max_power)
 592                tdp = max_power;
 593
 594        power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
 595
 596        /* Set long term power limit to TDP */
 597        limit.lo = 0;
 598        limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
 599        limit.lo |= PKG_POWER_LIMIT_EN;
 600        limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 601                PKG_POWER_LIMIT_TIME_SHIFT;
 602
 603        /* Set short term power limit to 1.25 * TDP */
 604        limit.hi = 0;
 605        limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
 606        limit.hi |= PKG_POWER_LIMIT_EN;
 607        /* Power limit 2 time is only programmable on server SKU */
 608
 609        msr_write(MSR_PKG_POWER_LIMIT, limit);
 610
 611        /* Set power limit values in MCHBAR as well */
 612        writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
 613        writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
 614
 615        /* Set DDR RAPL power limit by copying from MMIO to MSR */
 616        msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
 617        msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
 618        msr_write(MSR_DDR_RAPL_LIMIT, msr);
 619
 620        /* Use nominal TDP values for CPUs with configurable TDP */
 621        if (cpu_config_tdp_levels()) {
 622                msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
 623                limit.hi = 0;
 624                limit.lo = msr.lo & 0xff;
 625                msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
 626        }
 627}
 628
 629static int broadwell_get_info(const struct udevice *dev, struct cpu_info *info)
 630{
 631        return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
 632}
 633
 634static int broadwell_get_count(const struct udevice *dev)
 635{
 636        return 4;
 637}
 638
 639static int cpu_x86_broadwell_probe(struct udevice *dev)
 640{
 641        if (dev->seq == 0) {
 642                cpu_core_init(dev);
 643                return broadwell_init(dev);
 644        }
 645
 646        return 0;
 647}
 648
 649static const struct cpu_ops cpu_x86_broadwell_ops = {
 650        .get_desc       = cpu_x86_get_desc,
 651        .get_info       = broadwell_get_info,
 652        .get_count      = broadwell_get_count,
 653        .get_vendor     = cpu_x86_get_vendor,
 654};
 655
 656static const struct udevice_id cpu_x86_broadwell_ids[] = {
 657        { .compatible = "intel,core-i3-gen5" },
 658        { }
 659};
 660
 661U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
 662        .name           = "cpu_x86_broadwell",
 663        .id             = UCLASS_CPU,
 664        .of_match       = cpu_x86_broadwell_ids,
 665        .bind           = cpu_x86_bind,
 666        .probe          = cpu_x86_broadwell_probe,
 667        .ops            = &cpu_x86_broadwell_ops,
 668        .priv_auto_alloc_size   = sizeof(struct cpu_broadwell_priv),
 669        .flags          = DM_FLAG_PRE_RELOC,
 670};
 671