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7#include <common.h>
8#include <init.h>
9#include <net.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <env.h>
15#include <malloc.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/mach-imx/sata.h>
19#include <asm/mach-imx/mxc_i2c.h>
20#include <asm/mach-imx/boot_mode.h>
21#include <asm/arch/crm_regs.h>
22#include <asm/arch/sys_proto.h>
23#include <mmc.h>
24#include <fsl_esdhc_imx.h>
25#include <netdev.h>
26#include <i2c.h>
27#include <pca953x.h>
28#include <asm/gpio.h>
29#include <phy.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
34
35#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
39 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
43 PAD_CTL_HYS)
44
45#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
46 PAD_CTL_SRE_FAST)
47
48#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
49 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50
51int dram_init(void)
52{
53 gd->ram_size = imx_ddr_size();
54
55 return 0;
56}
57
58static iomux_v3_cfg_t const uart1_pads[] = {
59 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
61};
62
63static void setup_iomux_uart(void)
64{
65 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
66}
67
68static iomux_v3_cfg_t const enet_pads[] = {
69 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
86};
87
88static void setup_iomux_enet(void)
89{
90 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
91}
92
93static iomux_v3_cfg_t const ecspi1_pads[] = {
94 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
95 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
96 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
97 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
98 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
99};
100
101static void setup_iomux_spi(void)
102{
103 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
104}
105
106int board_spi_cs_gpio(unsigned bus, unsigned cs)
107{
108 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
109}
110
111static iomux_v3_cfg_t const feature_pads[] = {
112
113 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
114
115
116 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
117};
118
119static void setup_iomux_features(void)
120{
121 imx_iomux_v3_setup_multiple_pads(feature_pads,
122 ARRAY_SIZE(feature_pads));
123}
124
125#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
126
127
128static struct i2c_pads_info i2c_pad_info1 = {
129 .scl = {
130 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
131 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
132 .gp = IMX_GPIO_NR(2, 30)
133 },
134 .sda = {
135 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
136 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
137 .gp = IMX_GPIO_NR(3, 16)
138 }
139};
140
141
142static struct i2c_pads_info i2c_pad_info2 = {
143 .scl = {
144 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
145 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
146 .gp = IMX_GPIO_NR(3, 17)
147 },
148 .sda = {
149 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
150 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
151 .gp = IMX_GPIO_NR(3, 18)
152 }
153};
154
155static void setup_iomux_i2c(void)
156{
157 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
158 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
159}
160
161static void ccgr_init(void)
162{
163 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
164
165 writel(0x00C03F3F, &ccm->CCGR0);
166 writel(0x0030FC33, &ccm->CCGR1);
167 writel(0x0FFFC000, &ccm->CCGR2);
168 writel(0x3FF00000, &ccm->CCGR3);
169 writel(0x00FFF300, &ccm->CCGR4);
170 writel(0x0F0000C3, &ccm->CCGR5);
171 writel(0x000003FF, &ccm->CCGR6);
172}
173
174int board_early_init_f(void)
175{
176 ccgr_init();
177 gpr_init();
178
179 setup_iomux_uart();
180 setup_iomux_spi();
181 setup_iomux_i2c();
182 setup_iomux_features();
183
184 return 0;
185}
186
187static iomux_v3_cfg_t const usdhc3_pads[] = {
188 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
190 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
192 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199};
200
201iomux_v3_cfg_t const usdhc4_pads[] = {
202 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
203 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
204 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
205 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
206 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
207 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
208};
209
210int board_mmc_getcd(struct mmc *mmc)
211{
212 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
213 int ret;
214
215 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
216 gpio_direction_input(IMX_GPIO_NR(4, 5));
217 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
218 } else {
219 gpio_direction_input(IMX_GPIO_NR(1, 5));
220 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
221 }
222
223 return ret;
224}
225
226struct fsl_esdhc_cfg usdhc_cfg[2] = {
227 {USDHC3_BASE_ADDR},
228 {USDHC4_BASE_ADDR},
229};
230
231int board_mmc_init(struct bd_info *bis)
232{
233 int ret;
234 u32 index = 0;
235
236 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
237 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
238
239 usdhc_cfg[0].max_bus_width = 8;
240 usdhc_cfg[1].max_bus_width = 4;
241
242 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
243 switch (index) {
244 case 0:
245 imx_iomux_v3_setup_multiple_pads(
246 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
247 break;
248 case 1:
249 imx_iomux_v3_setup_multiple_pads(
250 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
251 break;
252 default:
253 printf("Warning: you configured more USDHC controllers"
254 "(%d) then supported by the board (%d)\n",
255 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
256 return -EINVAL;
257 }
258
259 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
260 if (ret)
261 return ret;
262 }
263
264 return 0;
265}
266
267static void leds_on(void)
268{
269
270 i2c_set_bus_num(2);
271 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
272 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
273}
274
275static void backlight_lcd_off(void)
276{
277 unsigned gpio = IMX_GPIO_NR(2, 0);
278 gpio_direction_output(gpio, 0);
279
280 gpio = IMX_GPIO_NR(2, 3);
281 gpio_direction_output(gpio, 0);
282}
283
284int board_eth_init(struct bd_info *bis)
285{
286 uint32_t base = IMX_FEC_BASE;
287 struct mii_dev *bus = NULL;
288 struct phy_device *phydev = NULL;
289 int ret;
290
291 setup_iomux_enet();
292
293 bus = fec_get_miibus(base, -1);
294 if (!bus)
295 return -EINVAL;
296
297
298 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
299 if (!phydev) {
300 ret = -EINVAL;
301 goto free_bus;
302 }
303
304
305 if (phydev->addr == 0)
306 env_set("boardver", "");
307 else
308 env_set("boardver", "mr");
309
310 printf("using phy at %d\n", phydev->addr);
311 ret = fec_probe(bis, -1, base, bus, phydev);
312 if (ret)
313 goto free_phydev;
314
315 return 0;
316
317free_phydev:
318 free(phydev);
319free_bus:
320 free(bus);
321 return ret;
322}
323
324int board_init(void)
325{
326 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
327
328 backlight_lcd_off();
329
330 leds_on();
331
332#ifdef CONFIG_SATA
333 setup_sata();
334#endif
335
336 return 0;
337}
338
339int checkboard(void)
340{
341 puts("Board: "CONFIG_SYS_BOARD"\n");
342 return 0;
343}
344
345#ifdef CONFIG_CMD_BMODE
346static const struct boot_mode board_boot_modes[] = {
347
348 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
349 {NULL, 0},
350};
351#endif
352
353int misc_init_r(void)
354{
355#ifdef CONFIG_CMD_BMODE
356 add_board_boot_modes(board_boot_modes);
357#endif
358 return 0;
359}
360
