LXR uboot/board/freescale/common/pfuze.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2014 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <errno.h>
   8#include <power/pmic.h>
   9#include <power/pfuze100_pmic.h>
  10
  11#ifndef CONFIG_DM_PMIC_PFUZE100
  12int pfuze_mode_init(struct pmic *p, u32 mode)
  13{
  14        unsigned char offset, i, switch_num;
  15        u32 id;
  16        int ret;
  17
  18        pmic_reg_read(p, PFUZE100_DEVICEID, &id);
  19        id = id & 0xf;
  20
  21        if (id == 0) {
  22                switch_num = 6;
  23                offset = PFUZE100_SW1CMODE;
  24        } else if (id == 1) {
  25                switch_num = 4;
  26                offset = PFUZE100_SW2MODE;
  27        } else {
  28                printf("Not supported, id=%d\n", id);
  29                return -EINVAL;
  30        }
  31
  32        ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
  33        if (ret < 0) {
  34                printf("Set SW1AB mode error!\n");
  35                return ret;
  36        }
  37
  38        for (i = 0; i < switch_num - 1; i++) {
  39                ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
  40                if (ret < 0) {
  41                        printf("Set switch 0x%x mode error!\n",
  42                               offset + i * SWITCH_SIZE);
  43                        return ret;
  44                }
  45        }
  46
  47        return ret;
  48}
  49
  50struct pmic *pfuze_common_init(unsigned char i2cbus)
  51{
  52        struct pmic *p;
  53        int ret;
  54        unsigned int reg;
  55
  56        ret = power_pfuze100_init(i2cbus);
  57        if (ret)
  58                return NULL;
  59
  60        p = pmic_get("PFUZE100");
  61        ret = pmic_probe(p);
  62        if (ret)
  63                return NULL;
  64
  65        pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  66        printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
  67
  68        /* Set SW1AB stanby volage to 0.975V */
  69        pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  70        reg &= ~SW1x_STBY_MASK;
  71        reg |= SW1x_0_975V;
  72        pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
  73
  74        /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  75        pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
  76        reg &= ~SW1xCONF_DVSSPEED_MASK;
  77        reg |= SW1xCONF_DVSSPEED_4US;
  78        pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
  79
  80        /* Set SW1C standby voltage to 0.975V */
  81        pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
  82        reg &= ~SW1x_STBY_MASK;
  83        reg |= SW1x_0_975V;
  84        pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
  85
  86        /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
  87        pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
  88        reg &= ~SW1xCONF_DVSSPEED_MASK;
  89        reg |= SW1xCONF_DVSSPEED_4US;
  90        pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
  91
  92        return p;
  93}
  94#else
  95int pfuze_mode_init(struct udevice *dev, u32 mode)
  96{
  97        unsigned char offset, i, switch_num;
  98        u32 id;
  99        int ret;
 100
 101        id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 102        id = id & 0xf;
 103
 104        if (id == 0) {
 105                switch_num = 6;
 106                offset = PFUZE100_SW1CMODE;
 107        } else if (id == 1) {
 108                switch_num = 4;
 109                offset = PFUZE100_SW2MODE;
 110        } else {
 111                printf("Not supported, id=%d\n", id);
 112                return -EINVAL;
 113        }
 114
 115        ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
 116        if (ret < 0) {
 117                printf("Set SW1AB mode error!\n");
 118                return ret;
 119        }
 120
 121        for (i = 0; i < switch_num - 1; i++) {
 122                ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
 123                if (ret < 0) {
 124                        printf("Set switch 0x%x mode error!\n",
 125                               offset + i * SWITCH_SIZE);
 126                        return ret;
 127                }
 128        }
 129
 130        return ret;
 131}
 132
 133struct udevice *pfuze_common_init(void)
 134{
 135        struct udevice *dev;
 136        int ret;
 137        unsigned int reg, dev_id, rev_id;
 138
 139        ret = pmic_get("pfuze100@8", &dev);
 140        if (ret == -ENODEV)
 141                return NULL;
 142
 143        dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 144        rev_id = pmic_reg_read(dev, PFUZE100_REVID);
 145        printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 146
 147        /* Set SW1AB stanby volage to 0.975V */
 148        reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
 149        reg &= ~SW1x_STBY_MASK;
 150        reg |= SW1x_0_975V;
 151        pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
 152
 153        /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 154        reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
 155        reg &= ~SW1xCONF_DVSSPEED_MASK;
 156        reg |= SW1xCONF_DVSSPEED_4US;
 157        pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
 158
 159        /* Set SW1C standby voltage to 0.975V */
 160        reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
 161        reg &= ~SW1x_STBY_MASK;
 162        reg |= SW1x_0_975V;
 163        pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
 164
 165        /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 166        reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
 167        reg &= ~SW1xCONF_DVSSPEED_MASK;
 168        reg |= SW1xCONF_DVSSPEED_4US;
 169        pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 170
 171        return dev;
 172}
 173#endif
 174