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7#include <common.h>
8#include <clock_legacy.h>
9#include <fdt_support.h>
10#include <i2c.h>
11#include <init.h>
12#include <log.h>
13#include <asm/io.h>
14#include <asm/arch/immap_ls102xa.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/fsl_serdes.h>
17#include <asm/arch/ls102xa_soc.h>
18#include <asm/arch/ls102xa_devdis.h>
19#include <hwconfig.h>
20#include <mmc.h>
21#include <fsl_csu.h>
22#include <fsl_ifc.h>
23#include <fsl_sec.h>
24#include <spl.h>
25#include <fsl_devdis.h>
26#include <fsl_validate.h>
27#include <fsl_ddr.h>
28#include "../common/sleep.h"
29#include "../common/qixis.h"
30#include "ls1021aqds_qixis.h"
31#ifdef CONFIG_U_QE
32#include <fsl_qe.h>
33#endif
34
35#define PIN_MUX_SEL_CAN 0x03
36#define PIN_MUX_SEL_IIC2 0xa0
37#define PIN_MUX_SEL_RGMII 0x00
38#define PIN_MUX_SEL_SAI 0x0c
39#define PIN_MUX_SEL_SDHC 0x00
40
41#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
42#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
43enum {
44 MUX_TYPE_CAN,
45 MUX_TYPE_IIC2,
46 MUX_TYPE_RGMII,
47 MUX_TYPE_SAI,
48 MUX_TYPE_SDHC,
49 MUX_TYPE_SD_PCI4,
50 MUX_TYPE_SD_PC_SA_SG_SG,
51 MUX_TYPE_SD_PC_SA_PC_SG,
52 MUX_TYPE_SD_PC_SG_SG,
53};
54
55enum {
56 GE0_CLK125,
57 GE2_CLK125,
58 GE1_CLK125,
59};
60
61int checkboard(void)
62{
63#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
64 char buf[64];
65#endif
66#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
67 u8 sw;
68#endif
69
70 puts("Board: LS1021AQDS\n");
71
72#ifdef CONFIG_SD_BOOT
73 puts("SD\n");
74#elif CONFIG_QSPI_BOOT
75 puts("QSPI\n");
76#else
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
79
80 if (sw < 0x8)
81 printf("vBank: %d\n", sw);
82 else if (sw == 0x8)
83 puts("PromJet\n");
84 else if (sw == 0x9)
85 puts("NAND\n");
86 else if (sw == 0x15)
87 printf("IFCCard\n");
88 else
89 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
90#endif
91
92#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
93 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
94 QIXIS_READ(id), QIXIS_READ(arch));
95
96 printf("FPGA: v%d (%s), build %d\n",
97 (int)QIXIS_READ(scver), qixis_read_tag(buf),
98 (int)qixis_read_minor());
99#endif
100
101 return 0;
102}
103
104unsigned long get_board_sys_clk(void)
105{
106 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
107
108 switch (sysclk_conf & 0x0f) {
109 case QIXIS_SYSCLK_64:
110 return 64000000;
111 case QIXIS_SYSCLK_83:
112 return 83333333;
113 case QIXIS_SYSCLK_100:
114 return 100000000;
115 case QIXIS_SYSCLK_125:
116 return 125000000;
117 case QIXIS_SYSCLK_133:
118 return 133333333;
119 case QIXIS_SYSCLK_150:
120 return 150000000;
121 case QIXIS_SYSCLK_160:
122 return 160000000;
123 case QIXIS_SYSCLK_166:
124 return 166666666;
125 }
126 return 66666666;
127}
128
129unsigned long get_board_ddr_clk(void)
130{
131 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
132
133 switch ((ddrclk_conf & 0x30) >> 4) {
134 case QIXIS_DDRCLK_100:
135 return 100000000;
136 case QIXIS_DDRCLK_125:
137 return 125000000;
138 case QIXIS_DDRCLK_133:
139 return 133333333;
140 }
141 return 66666666;
142}
143
144int select_i2c_ch_pca9547(u8 ch, int bus_num)
145{
146 int ret;
147#ifdef CONFIG_DM_I2C
148 struct udevice *dev;
149
150 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
151 1, &dev);
152 if (ret) {
153 printf("%s: Cannot find udev for a bus %d\n", __func__,
154 bus_num);
155 return ret;
156 }
157 ret = dm_i2c_write(dev, 0, &ch, 1);
158#else
159 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
160#endif
161 if (ret) {
162 puts("PCA: failed to select proper channel\n");
163 return ret;
164 }
165
166 return 0;
167}
168
169int dram_init(void)
170{
171
172
173
174
175
176
177
178 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
179 return fsl_initdram();
180}
181
182int board_early_init_f(void)
183{
184 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
185
186#ifdef CONFIG_TSEC_ENET
187
188 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
189#endif
190
191#ifdef CONFIG_FSL_IFC
192 init_early_memctl_regs();
193#endif
194
195 arch_soc_init();
196
197#if defined(CONFIG_DEEP_SLEEP)
198 if (is_warm_boot())
199 fsl_dp_disable_console();
200#endif
201
202 return 0;
203}
204
205#ifdef CONFIG_SPL_BUILD
206void board_init_f(ulong dummy)
207{
208#ifdef CONFIG_NAND_BOOT
209 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
210 u32 porsr1, pinctl;
211
212
213
214
215
216
217 porsr1 = in_be32(&gur->porsr1);
218 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
219 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
220 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
221 pinctl);
222#endif
223
224
225 memset(__bss_start, 0, __bss_end - __bss_start);
226
227#ifdef CONFIG_FSL_IFC
228 init_early_memctl_regs();
229#endif
230
231 get_clocks();
232
233#if defined(CONFIG_DEEP_SLEEP)
234 if (is_warm_boot())
235 fsl_dp_disable_console();
236#endif
237
238 preloader_console_init();
239
240#ifdef CONFIG_SPL_I2C_SUPPORT
241 i2c_init_all();
242#endif
243
244 timer_init();
245 dram_init();
246
247
248#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
249 enable_layerscape_ns_access();
250#endif
251
252 board_init_r(NULL, 0);
253}
254#endif
255
256void config_etseccm_source(int etsec_gtx_125_mux)
257{
258 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
259
260 switch (etsec_gtx_125_mux) {
261 case GE0_CLK125:
262 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
263 debug("etseccm set to GE0_CLK125\n");
264 break;
265
266 case GE2_CLK125:
267 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
268 debug("etseccm set to GE2_CLK125\n");
269 break;
270
271 case GE1_CLK125:
272 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
273 debug("etseccm set to GE1_CLK125\n");
274 break;
275
276 default:
277 printf("Error! trying to set etseccm to invalid value\n");
278 break;
279 }
280}
281
282int config_board_mux(int ctrl_type)
283{
284 u8 reg12, reg14;
285
286 reg12 = QIXIS_READ(brdcfg[12]);
287 reg14 = QIXIS_READ(brdcfg[14]);
288
289 switch (ctrl_type) {
290 case MUX_TYPE_CAN:
291 config_etseccm_source(GE2_CLK125);
292 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
293 break;
294 case MUX_TYPE_IIC2:
295 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
296 break;
297 case MUX_TYPE_RGMII:
298 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
299 break;
300 case MUX_TYPE_SAI:
301 config_etseccm_source(GE2_CLK125);
302 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
303 break;
304 case MUX_TYPE_SDHC:
305 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
306 break;
307 case MUX_TYPE_SD_PCI4:
308 reg12 = 0x38;
309 break;
310 case MUX_TYPE_SD_PC_SA_SG_SG:
311 reg12 = 0x01;
312 break;
313 case MUX_TYPE_SD_PC_SA_PC_SG:
314 reg12 = 0x01;
315 break;
316 case MUX_TYPE_SD_PC_SG_SG:
317 reg12 = 0x21;
318 break;
319 default:
320 printf("Wrong mux interface type\n");
321 return -1;
322 }
323
324 QIXIS_WRITE(brdcfg[12], reg12);
325 QIXIS_WRITE(brdcfg[14], reg14);
326
327 return 0;
328}
329
330int config_serdes_mux(void)
331{
332 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
333 u32 cfg;
334
335 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
336 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
337
338 switch (cfg) {
339 case 0x0:
340 config_board_mux(MUX_TYPE_SD_PCI4);
341 break;
342 case 0x30:
343 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
344 break;
345 case 0x60:
346 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
347 break;
348 case 0x70:
349 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
350 break;
351 default:
352 printf("SRDS1 prtcl:0x%x\n", cfg);
353 break;
354 }
355
356 return 0;
357}
358
359#ifdef CONFIG_BOARD_LATE_INIT
360int board_late_init(void)
361{
362#ifdef CONFIG_CHAIN_OF_TRUST
363 fsl_setenv_chain_of_trust();
364#endif
365
366 return 0;
367}
368#endif
369
370int misc_init_r(void)
371{
372 int conflict_flag;
373
374
375 conflict_flag = 0;
376 if (hwconfig("sdhc"))
377 conflict_flag++;
378 if (hwconfig("iic2"))
379 conflict_flag++;
380 if (conflict_flag > 1) {
381 printf("WARNING: pin conflict !\n");
382 return 0;
383 }
384
385 conflict_flag = 0;
386 if (hwconfig("rgmii"))
387 conflict_flag++;
388 if (hwconfig("can"))
389 conflict_flag++;
390 if (hwconfig("sai"))
391 conflict_flag++;
392 if (conflict_flag > 1) {
393 printf("WARNING: pin conflict !\n");
394 return 0;
395 }
396
397 if (hwconfig("can"))
398 config_board_mux(MUX_TYPE_CAN);
399 else if (hwconfig("rgmii"))
400 config_board_mux(MUX_TYPE_RGMII);
401 else if (hwconfig("sai"))
402 config_board_mux(MUX_TYPE_SAI);
403
404 if (hwconfig("iic2"))
405 config_board_mux(MUX_TYPE_IIC2);
406 else if (hwconfig("sdhc"))
407 config_board_mux(MUX_TYPE_SDHC);
408
409#ifdef CONFIG_FSL_DEVICE_DISABLE
410 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
411#endif
412#ifdef CONFIG_FSL_CAAM
413 return sec_init();
414#endif
415 return 0;
416}
417
418int board_init(void)
419{
420#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
421 erratum_a010315();
422#endif
423#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
424 erratum_a009942_check_cpo();
425#endif
426
427 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
428
429#ifndef CONFIG_SYS_FSL_NO_SERDES
430 fsl_serdes_init();
431 config_serdes_mux();
432#endif
433
434 ls102xa_smmu_stream_id_init();
435
436#ifdef CONFIG_U_QE
437 u_qe_init();
438#endif
439
440 return 0;
441}
442
443#if defined(CONFIG_DEEP_SLEEP)
444void board_sleep_prepare(void)
445{
446#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
447 enable_layerscape_ns_access();
448#endif
449}
450#endif
451
452int ft_board_setup(void *blob, struct bd_info *bd)
453{
454 ft_cpu_setup(blob, bd);
455
456#ifdef CONFIG_PCI
457 ft_pci_setup(blob, bd);
458#endif
459
460 return 0;
461}
462
463u8 flash_read8(void *addr)
464{
465 return __raw_readb(addr + 1);
466}
467
468void flash_write16(u16 val, void *addr)
469{
470 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
471
472 __raw_writew(shftval, addr);
473}
474
475u16 flash_read16(void *addr)
476{
477 u16 val = __raw_readw(addr);
478
479 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
480}
481
