LXR uboot/board/renesas/lager/lager.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * board/renesas/lager/lager.c
   4 *     This file is lager board support.
   5 *
   6 * Copyright (C) 2013 Renesas Electronics Corporation
   7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   8 */
   9
  10#include <common.h>
  11#include <cpu_func.h>
  12#include <env.h>
  13#include <env_internal.h>
  14#include <hang.h>
  15#include <init.h>
  16#include <malloc.h>
  17#include <netdev.h>
  18#include <dm.h>
  19#include <dm/platform_data/serial_sh.h>
  20#include <asm/processor.h>
  21#include <asm/mach-types.h>
  22#include <asm/io.h>
  23#include <linux/bitops.h>
  24#include <linux/delay.h>
  25#include <linux/errno.h>
  26#include <asm/arch/sys_proto.h>
  27#include <asm/gpio.h>
  28#include <asm/arch/rmobile.h>
  29#include <asm/arch/rcar-mstp.h>
  30#include <asm/arch/mmc.h>
  31#include <asm/arch/sh_sdhi.h>
  32#include <miiphy.h>
  33#include <i2c.h>
  34#include <mmc.h>
  35#include "qos.h"
  36
  37DECLARE_GLOBAL_DATA_PTR;
  38
  39#define CLK2MHZ(clk)    (clk / 1000 / 1000)
  40void s_init(void)
  41{
  42        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  43        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  44
  45        /* Watchdog init */
  46        writel(0xA5A5A500, &rwdt->rwtcsra);
  47        writel(0xA5A5A500, &swdt->swtcsra);
  48
  49        /* CPU frequency setting. Set to 1.4GHz */
  50        if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
  51                u32 stat = 0;
  52                u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
  53                        << PLL0_STC_BIT;
  54                clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  55
  56                do {
  57                        stat = readl(PLLECR) & PLL0ST;
  58                } while (stat == 0x0);
  59        }
  60
  61        /* QoS(Quality-of-Service) Init */
  62        qos_init();
  63}
  64
  65#define TMU0_MSTP125    BIT(25)
  66
  67#define SD1CKCR         0xE6150078
  68#define SD2CKCR         0xE615026C
  69#define SD_97500KHZ     0x7
  70
  71int board_early_init_f(void)
  72{
  73        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  74
  75        /*
  76         * SD0 clock is set to 97.5MHz by default.
  77         * Set SD1 and SD2 to the 97.5MHz as well.
  78         */
  79        writel(SD_97500KHZ, SD1CKCR);
  80        writel(SD_97500KHZ, SD2CKCR);
  81
  82        return 0;
  83}
  84
  85#define ETHERNET_PHY_RESET      185     /* GPIO 5 31 */
  86
  87int board_init(void)
  88{
  89        /* adress of boot parameters */
  90        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  91
  92        /* Force ethernet PHY out of reset */
  93        gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  94        gpio_direction_output(ETHERNET_PHY_RESET, 0);
  95        mdelay(10);
  96        gpio_direction_output(ETHERNET_PHY_RESET, 1);
  97
  98        return 0;
  99}
 100
 101int dram_init(void)
 102{
 103        if (fdtdec_setup_mem_size_base() != 0)
 104                return -EINVAL;
 105
 106        return 0;
 107}
 108
 109int dram_init_banksize(void)
 110{
 111        fdtdec_setup_memory_banksize();
 112
 113        return 0;
 114}
 115
 116/* KSZ8041NL/RNL */
 117#define PHY_CONTROL1            0x1E
 118#define PHY_LED_MODE            0xC000
 119#define PHY_LED_MODE_ACK        0x4000
 120int board_phy_config(struct phy_device *phydev)
 121{
 122        int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 123        ret &= ~PHY_LED_MODE;
 124        ret |= PHY_LED_MODE_ACK;
 125        ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 126
 127        return 0;
 128}
 129
 130void reset_cpu(ulong addr)
 131{
 132        struct udevice *dev;
 133        const u8 pmic_bus = 2;
 134        const u8 pmic_addr = 0x58;
 135        u8 data;
 136        int ret;
 137
 138        ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 139        if (ret)
 140                hang();
 141
 142        ret = dm_i2c_read(dev, 0x13, &data, 1);
 143        if (ret)
 144                hang();
 145
 146        data |= BIT(1);
 147
 148        ret = dm_i2c_write(dev, 0x13, &data, 1);
 149        if (ret)
 150                hang();
 151}
 152
 153enum env_location env_get_location(enum env_operation op, int prio)
 154{
 155        const u32 load_magic = 0xb33fc0de;
 156
 157        /* Block environment access if loaded using JTAG */
 158        if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
 159            (op != ENVOP_INIT))
 160                return ENVL_UNKNOWN;
 161
 162        if (prio)
 163                return ENVL_UNKNOWN;
 164
 165        return ENVL_SPI_FLASH;
 166}
 167