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8#include <common.h>
9#include <cpu_func.h>
10#include <init.h>
11#include <malloc.h>
12#include <dm/platform_data/serial_sh.h>
13#include <asm/processor.h>
14#include <asm/mach-types.h>
15#include <asm/io.h>
16#include <linux/bitops.h>
17#include <linux/errno.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/gpio.h>
20#include <asm/arch/rmobile.h>
21#include <asm/arch/rcar-mstp.h>
22
23#include <spl.h>
24
25#define TMU0_MSTP125 BIT(25)
26#define SCIF0_MSTP721 BIT(21)
27#define QSPI_MSTP917 BIT(17)
28
29#define SD2CKCR 0xE615026C
30#define SD_97500KHZ 0x7
31
32struct reg_config {
33 u16 off;
34 u32 val;
35};
36
37static void dbsc_wait(u16 reg)
38{
39 static const u32 dbsc3_0_base = DBSC3_0_BASE;
40
41 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
42 ;
43}
44
45static void spl_init_sys(void)
46{
47 u32 r0 = 0;
48
49 writel(0xa5a5a500, 0xe6020004);
50 writel(0xa5a5a500, 0xe6030004);
51
52 asm volatile(
53
54 "mcr 15, 0, %0, cr7, cr5, 0 \n"
55
56 "mcr 15, 0, %0, cr7, cr5, 6 \n"
57
58 "mrc 15, 0, %0, cr1, cr0, 0 \n"
59 "orr %0, #0x1800 \n"
60 "mcr 15, 0, %0, cr1, cr0, 0 \n"
61 "isb sy \n"
62 :"=r"(r0));
63}
64
65static void spl_init_pfc(void)
66{
67 static const struct reg_config pfc_with_unlock[] = {
68 { 0x0090, 0x00000000 },
69 { 0x0094, 0x00000000 },
70 { 0x0098, 0xc0000000 },
71 { 0x0020, 0x00000000 },
72 { 0x0024, 0x00000000 },
73 { 0x0028, 0x00000000 },
74 { 0x002c, 0x20000000 },
75 { 0x0030, 0x00001249 },
76 { 0x0034, 0x00000278 },
77 { 0x0038, 0x00000841 },
78 { 0x003c, 0x00000000 },
79 { 0x0040, 0x00000000 },
80 { 0x0044, 0x10000000 },
81 { 0x0048, 0x00000001 },
82 { 0x004c, 0x0004aab0 },
83 { 0x0050, 0x37301b00 },
84 { 0x0054, 0x00048da3 },
85 { 0x0058, 0x089044a1 },
86 { 0x005c, 0x2a3a55b4 },
87 { 0x0160, 0x00000003 },
88 { 0x0004, 0xffffffff },
89 { 0x0008, 0x2aef3fff },
90 { 0x000c, 0x3fffffff },
91 { 0x0010, 0xff7fc07f },
92 { 0x0014, 0x7f3ff3f8 },
93 { 0x0018, 0x1cfdfff7 },
94 };
95
96 static const struct reg_config pfc_without_unlock[] = {
97 { 0x0100, 0x1fffffff },
98 { 0x0104, 0xffff0318 },
99 { 0x0108, 0x387fffe1 },
100 { 0x010c, 0x00803f80 },
101 { 0x0110, 0x1520009f },
102 { 0x0114, 0x00000000 },
103 { 0x0118, 0x00000000 },
104 };
105
106 static const u32 pfc_base = 0xe6060000;
107
108 unsigned int i;
109
110 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
111 writel(~pfc_with_unlock[i].val, pfc_base);
112 writel(pfc_with_unlock[i].val,
113 pfc_base | pfc_with_unlock[i].off);
114 }
115
116 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
117 writel(pfc_without_unlock[i].val,
118 pfc_base | pfc_without_unlock[i].off);
119}
120
121static void spl_init_gpio(void)
122{
123 static const u16 gpio_offs[] = {
124 0x1000, 0x3000, 0x4000, 0x5000
125 };
126
127 static const struct reg_config gpio_set[] = {
128 { 0x4000, 0x00c00000 },
129 { 0x5000, 0x63020000 },
130 };
131
132 static const struct reg_config gpio_clr[] = {
133 { 0x1000, 0x00000000 },
134 { 0x3000, 0x00000000 },
135 { 0x4000, 0x00c00000 },
136 { 0x5000, 0xe3020000 },
137 };
138
139 static const u32 gpio_base = 0xe6050000;
140
141 unsigned int i;
142
143 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
144 writel(0, gpio_base | 0x20 | gpio_offs[i]);
145
146 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
147 writel(0, gpio_base | 0x00 | gpio_offs[i]);
148
149 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
150 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
151
152 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
153 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
154}
155
156static void spl_init_lbsc(void)
157{
158 static const struct reg_config lbsc_config[] = {
159 { 0x00, 0x00000020 },
160 { 0x08, 0x00002020 },
161 { 0x30, 0x02150326 },
162 { 0x38, 0x077f077f },
163 };
164
165 static const u16 lbsc_offs[] = {
166 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
167 };
168
169 static const u32 lbsc_base = 0xfec00200;
170
171 unsigned int i;
172
173 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
174 writel(lbsc_config[i].val,
175 lbsc_base | lbsc_config[i].off);
176 writel(lbsc_config[i].val,
177 lbsc_base | (lbsc_config[i].off + 4));
178 }
179
180 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
181 writel(0, lbsc_base | lbsc_offs[i]);
182}
183
184static void spl_init_dbsc(void)
185{
186 static const struct reg_config dbsc_config1[] = {
187 { 0x0018, 0x21000000 },
188 { 0x0018, 0x11000000 },
189 { 0x0018, 0x10000000 },
190 { 0x0280, 0x0000a55a },
191 { 0x0290, 0x00000001 },
192 { 0x02a0, 0x80000000 },
193 { 0x0290, 0x00000004 },
194 };
195
196 static const struct reg_config dbsc_config4[] = {
197 { 0x0290, 0x00000010 },
198 { 0x02a0, 0xf004649b },
199 { 0x0290, 0x0000000f },
200 { 0x02a0, 0x00181ee4 },
201 { 0x0290, 0x00000060 },
202 { 0x02a0, 0x330657b2 },
203 { 0x0290, 0x00000001 },
204 { 0x02a0, 0x00000071 },
205 { 0x0020, 0x00000007 },
206 { 0x0024, 0x10030a02 },
207 { 0x0030, 0x00000001 },
208 { 0x00b0, 0x00000000 },
209 { 0x0040, 0x0000000b },
210 { 0x0044, 0x00000008 },
211 { 0x0048, 0x00000000 },
212 { 0x0050, 0x0000000b },
213 { 0x0054, 0x000c000b },
214 { 0x0058, 0x00000027 },
215 { 0x005c, 0x0000001c },
216 { 0x0060, 0x00000005 },
217 { 0x0064, 0x00000018 },
218 { 0x0068, 0x00000008 },
219 { 0x006c, 0x0000000c },
220 { 0x0070, 0x00000009 },
221 { 0x0074, 0x00000012 },
222 { 0x0078, 0x000000d0 },
223 { 0x007c, 0x00140005 },
224 { 0x0080, 0x00050004 },
225 { 0x0084, 0x70233005 },
226 { 0x0088, 0x000c0000 },
227 { 0x008c, 0x00000300 },
228 { 0x0090, 0x00000040 },
229 { 0x0100, 0x00000001 },
230 { 0x00c0, 0x00020001 },
231 { 0x00c8, 0x20082008 },
232 { 0x0380, 0x00020002 },
233 { 0x0390, 0x0000000f },
234 };
235
236 static const struct reg_config dbsc_config5[] = {
237 { 0x0244, 0x00000011 },
238 { 0x0290, 0x00000006 },
239 { 0x02a0, 0x0005c000 },
240 { 0x0290, 0x00000003 },
241 { 0x02a0, 0x0300c481 },
242 { 0x0290, 0x00000023 },
243 { 0x02a0, 0x00fdb6c0 },
244 { 0x0290, 0x00000011 },
245 { 0x02a0, 0x1000040b },
246 { 0x0290, 0x00000012 },
247 { 0x02a0, 0x9d5cbb66 },
248 { 0x0290, 0x00000013 },
249 { 0x02a0, 0x1a868300 },
250 { 0x0290, 0x00000014 },
251 { 0x02a0, 0x300214d8 },
252 { 0x0290, 0x00000015 },
253 { 0x02a0, 0x00000d70 },
254 { 0x0290, 0x00000016 },
255 { 0x02a0, 0x00000006 },
256 { 0x0290, 0x00000017 },
257 { 0x02a0, 0x00000018 },
258 { 0x0290, 0x0000001a },
259 { 0x02a0, 0x910035c7 },
260 { 0x0290, 0x00000004 },
261 };
262
263 static const struct reg_config dbsc_config6[] = {
264 { 0x0290, 0x00000001 },
265 { 0x02a0, 0x00000181 },
266 { 0x0018, 0x11000000 },
267 { 0x0290, 0x00000004 },
268 };
269
270 static const struct reg_config dbsc_config7[] = {
271 { 0x0290, 0x00000001 },
272 { 0x02a0, 0x0000fe01 },
273 { 0x0290, 0x00000004 },
274 };
275
276 static const struct reg_config dbsc_config8[] = {
277 { 0x0304, 0x00000000 },
278 { 0x00f4, 0x01004c20 },
279 { 0x00f8, 0x014000aa },
280 { 0x00e0, 0x00000140 },
281 { 0x00e4, 0x00081860 },
282 { 0x00e8, 0x00010000 },
283 { 0x0014, 0x00000001 },
284 { 0x0010, 0x00000001 },
285 { 0x0280, 0x00000000 },
286 };
287
288 static const u32 dbsc3_0_base = DBSC3_0_BASE;
289 unsigned int i;
290
291 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
292 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
293
294 dbsc_wait(0x2a0);
295
296 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
297 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
298
299 dbsc_wait(0x240);
300
301 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
302 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
303
304 dbsc_wait(0x2a0);
305
306 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
307 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
308
309 dbsc_wait(0x2a0);
310
311 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
312 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
313
314 dbsc_wait(0x2a0);
315
316 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
317 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
318
319}
320
321static void spl_init_qspi(void)
322{
323 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
324
325 static const u32 qspi_base = 0xe6b10000;
326
327 writeb(0x08, qspi_base + 0x00);
328 writeb(0x00, qspi_base + 0x01);
329 writeb(0x06, qspi_base + 0x02);
330 writeb(0x01, qspi_base + 0x0a);
331 writeb(0x00, qspi_base + 0x0b);
332 writeb(0x00, qspi_base + 0x0c);
333 writeb(0x00, qspi_base + 0x0d);
334 writeb(0x00, qspi_base + 0x0e);
335
336 writew(0xe080, qspi_base + 0x10);
337
338 writeb(0xc0, qspi_base + 0x18);
339 writeb(0x00, qspi_base + 0x18);
340 writeb(0x00, qspi_base + 0x08);
341 writeb(0x48, qspi_base + 0x00);
342}
343
344void board_init_f(ulong dummy)
345{
346 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
347 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
348
349
350
351
352
353 writel(SD_97500KHZ, SD2CKCR);
354
355 spl_init_sys();
356 spl_init_pfc();
357 spl_init_gpio();
358 spl_init_lbsc();
359 spl_init_dbsc();
360 spl_init_qspi();
361}
362
363void spl_board_init(void)
364{
365
366 preloader_console_init();
367}
368
369void board_boot_order(u32 *spl_boot_list)
370{
371 const u32 jtag_magic = 0x1337c0de;
372 const u32 load_magic = 0xb33fc0de;
373
374
375
376
377
378 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
379 printf("JTAG boot detected!\n");
380
381 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
382 ;
383
384 spl_boot_list[0] = BOOT_DEVICE_RAM;
385 spl_boot_list[1] = BOOT_DEVICE_NONE;
386
387 return;
388 }
389
390
391 spl_boot_list[0] = BOOT_DEVICE_SPI;
392 spl_boot_list[1] = BOOT_DEVICE_UART;
393 spl_boot_list[2] = BOOT_DEVICE_NONE;
394}
395
396void reset_cpu(ulong addr)
397{
398}
399
