LXR uboot/board/renesas/porter/porter.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * board/renesas/porter/porter.c
   4 *
   5 * Copyright (C) 2015 Renesas Electronics Corporation
   6 * Copyright (C) 2015 Cogent Embedded, Inc.
   7 */
   8
   9#include <common.h>
  10#include <cpu_func.h>
  11#include <env.h>
  12#include <hang.h>
  13#include <init.h>
  14#include <malloc.h>
  15#include <dm.h>
  16#include <dm/platform_data/serial_sh.h>
  17#include <env_internal.h>
  18#include <asm/processor.h>
  19#include <asm/mach-types.h>
  20#include <asm/io.h>
  21#include <linux/bitops.h>
  22#include <linux/delay.h>
  23#include <linux/errno.h>
  24#include <asm/arch/sys_proto.h>
  25#include <asm/gpio.h>
  26#include <asm/arch/rmobile.h>
  27#include <asm/arch/rcar-mstp.h>
  28#include <asm/arch/sh_sdhi.h>
  29#include <netdev.h>
  30#include <miiphy.h>
  31#include <i2c.h>
  32#include <div64.h>
  33#include "qos.h"
  34
  35DECLARE_GLOBAL_DATA_PTR;
  36
  37#define CLK2MHZ(clk)    (clk / 1000 / 1000)
  38void s_init(void)
  39{
  40        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  41        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  42        u32 stc;
  43
  44        /* Watchdog init */
  45        writel(0xA5A5A500, &rwdt->rwtcsra);
  46        writel(0xA5A5A500, &swdt->swtcsra);
  47
  48        /* CPU frequency setting. Set to 1.5GHz */
  49        stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  50        clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  51
  52        /* QoS */
  53        qos_init();
  54}
  55
  56#define TMU0_MSTP125    BIT(25)
  57
  58#define SD2CKCR         0xE615026C
  59#define SD_97500KHZ     0x7
  60
  61int board_early_init_f(void)
  62{
  63        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  64
  65        /*
  66         * SD0 clock is set to 97.5MHz by default.
  67         * Set SD2 to the 97.5MHz as well.
  68         */
  69        writel(SD_97500KHZ, SD2CKCR);
  70
  71        return 0;
  72}
  73
  74#define ETHERNET_PHY_RESET      176     /* GPIO 5 22 */
  75
  76int board_init(void)
  77{
  78        /* adress of boot parameters */
  79        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  80
  81        /* Force ethernet PHY out of reset */
  82        gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  83        gpio_direction_output(ETHERNET_PHY_RESET, 0);
  84        mdelay(10);
  85        gpio_direction_output(ETHERNET_PHY_RESET, 1);
  86
  87        return 0;
  88}
  89
  90int dram_init(void)
  91{
  92        if (fdtdec_setup_mem_size_base() != 0)
  93                return -EINVAL;
  94
  95        return 0;
  96}
  97
  98int dram_init_banksize(void)
  99{
 100        fdtdec_setup_memory_banksize();
 101
 102        return 0;
 103}
 104
 105/* porter has KSZ8041RNLI */
 106#define PHY_CONTROL1            0x1E
 107#define PHY_LED_MODE            0xC000
 108#define PHY_LED_MODE_ACK        0x4000
 109int board_phy_config(struct phy_device *phydev)
 110{
 111        int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 112        ret &= ~PHY_LED_MODE;
 113        ret |= PHY_LED_MODE_ACK;
 114        ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 115
 116        return 0;
 117}
 118
 119void reset_cpu(ulong addr)
 120{
 121        struct udevice *dev;
 122        const u8 pmic_bus = 6;
 123        const u8 pmic_addr = 0x5a;
 124        u8 data;
 125        int ret;
 126
 127        ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 128        if (ret)
 129                hang();
 130
 131        ret = dm_i2c_read(dev, 0x13, &data, 1);
 132        if (ret)
 133                hang();
 134
 135        data |= BIT(1);
 136
 137        ret = dm_i2c_write(dev, 0x13, &data, 1);
 138        if (ret)
 139                hang();
 140}
 141
 142enum env_location env_get_location(enum env_operation op, int prio)
 143{
 144        const u32 load_magic = 0xb33fc0de;
 145
 146        /* Block environment access if loaded using JTAG */
 147        if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
 148            (op != ENVOP_INIT))
 149                return ENVL_UNKNOWN;
 150
 151        if (prio)
 152                return ENVL_UNKNOWN;
 153
 154        return ENVL_SPI_FLASH;
 155}
 156