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10#include <init.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/sys_proto.h>
16#include <env.h>
17#include <fdt_support.h>
18#include <linux/errno.h>
19#include <asm/gpio.h>
20#include <asm/io.h>
21#include <asm/mach-imx/mxc_i2c.h>
22#include <asm/mach-imx/spi.h>
23#include <common.h>
24#include <fsl_esdhc_imx.h>
25#include <linux/libfdt.h>
26#include <i2c.h>
27#include <mmc.h>
28#include <power/pfuze100_pmic.h>
29#include <power/pmic.h>
30#include <spi_flash.h>
31
32#include "tqma6_bb.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44
45#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
46 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54
55int dram_init(void)
56{
57 gd->ram_size = imx_ddr_size();
58
59 return 0;
60}
61
62static const uint16_t tqma6_emmc_dsr = 0x0100;
63
64#ifndef CONFIG_DM_MMC
65
66static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
67 NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
68 NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
69 NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
71 NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
73 NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
75 NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
76 NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
77
78 NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
79};
80
81
82
83
84
85
86
87struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
88 .esdhc_base = USDHC3_BASE_ADDR,
89 .max_bus_width = 8,
90};
91
92int board_mmc_getcd(struct mmc *mmc)
93{
94 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
95 int ret = 0;
96
97 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
98
99 ret = 1;
100 else
101 ret = tqma6_bb_board_mmc_getcd(mmc);
102
103 return ret;
104}
105
106int board_mmc_getwp(struct mmc *mmc)
107{
108 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
109 int ret = 0;
110
111 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
112
113 ret = 0;
114 else
115 ret = tqma6_bb_board_mmc_getwp(mmc);
116
117 return ret;
118}
119
120int board_mmc_init(struct bd_info *bis)
121{
122 imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
123 ARRAY_SIZE(tqma6_usdhc3_pads));
124 tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
125 if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
126 puts("Warning: failed to initialize eMMC dev\n");
127 } else {
128 struct mmc *mmc = find_mmc_device(0);
129 if (mmc)
130 mmc_set_dsr(mmc, tqma6_emmc_dsr);
131 }
132
133 tqma6_bb_board_mmc_init(bis);
134
135 return 0;
136}
137#endif
138
139#ifndef CONFIG_DM_SPI
140static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
141
142 NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
143 NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
144 NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
145 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
146};
147
148#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
149
150static unsigned const tqma6_ecspi1_cs[] = {
151 TQMA6_SF_CS_GPIO,
152};
153
154__weak void tqma6_iomuxc_spi(void)
155{
156 unsigned i;
157
158 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
159 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
160 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
161 ARRAY_SIZE(tqma6_ecspi1_pads));
162}
163
164#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
165int board_spi_cs_gpio(unsigned bus, unsigned cs)
166{
167 return ((bus == CONFIG_SF_DEFAULT_BUS) &&
168 (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
169}
170#endif
171#endif
172
173#ifdef CONFIG_SYS_I2C
174static struct i2c_pads_info tqma6_i2c3_pads = {
175
176 .scl = {
177 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
178 I2C_PAD_CTRL),
179 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
180 I2C_PAD_CTRL),
181 .gp = IMX_GPIO_NR(1, 5)
182 },
183 .sda = {
184 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
185 I2C_PAD_CTRL),
186 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
187 I2C_PAD_CTRL),
188 .gp = IMX_GPIO_NR(1, 6)
189 }
190};
191
192static void tqma6_setup_i2c(void)
193{
194 int ret;
195
196
197
198
199 ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
200 if (ret)
201 printf("setup I2C3 failed: %d\n", ret);
202}
203#endif
204
205int board_early_init_f(void)
206{
207 return tqma6_bb_board_early_init_f();
208}
209
210int board_init(void)
211{
212
213 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
214
215#ifndef CONFIG_DM_SPI
216 tqma6_iomuxc_spi();
217#endif
218#ifdef CONFIG_SYS_I2C
219 tqma6_setup_i2c();
220#endif
221
222 tqma6_bb_board_init();
223
224 return 0;
225}
226
227static const char *tqma6_get_boardname(void)
228{
229 u32 cpurev = get_cpu_rev();
230
231 switch ((cpurev & 0xFF000) >> 12) {
232 case MXC_CPU_MX6SOLO:
233 return "TQMa6S";
234 break;
235 case MXC_CPU_MX6DL:
236 return "TQMa6DL";
237 break;
238 case MXC_CPU_MX6D:
239 return "TQMa6D";
240 break;
241 case MXC_CPU_MX6Q:
242 return "TQMa6Q";
243 break;
244 default:
245 return "??";
246 };
247}
248
249#ifdef CONFIG_POWER
250
251int power_init_board(void)
252{
253 struct pmic *p;
254 u32 reg, rev;
255
256 power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
257 p = pmic_get("PFUZE100");
258 if (p && !pmic_probe(p)) {
259 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
260 pmic_reg_read(p, PFUZE100_REVID, &rev);
261 printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
262 }
263
264 return 0;
265}
266#endif
267
268int board_late_init(void)
269{
270 env_set("board_name", tqma6_get_boardname());
271
272 tqma6_bb_board_late_init();
273
274 return 0;
275}
276
277int checkboard(void)
278{
279 printf("Board: %s on a %s\n", tqma6_get_boardname(),
280 tqma6_bb_get_boardname());
281 return 0;
282}
283
284
285
286
287#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
288#define MODELSTRLEN 32u
289int ft_board_setup(void *blob, struct bd_info *bd)
290{
291 char modelstr[MODELSTRLEN];
292
293 snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
294 tqma6_bb_get_boardname());
295 do_fixup_by_path_string(blob, "/", "model", modelstr);
296 fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
297
298 do_fixup_by_path_u32(blob,
299 "/soc/aips-bus@02100000/usdhc@02198000",
300 "dsr", tqma6_emmc_dsr, 2);
301 tqma6_bb_ft_board_setup(blob, bd);
302
303 return 0;
304}
305#endif
306
