LXR uboot/board/udoo/udoo.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4 *
   5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6 */
   7
   8#include <init.h>
   9#include <net.h>
  10#include <asm/arch/clock.h>
  11#include <asm/arch/imx-regs.h>
  12#include <asm/arch/iomux.h>
  13#include <env.h>
  14#include <malloc.h>
  15#include <asm/arch/mx6-pins.h>
  16#include <linux/delay.h>
  17#include <linux/errno.h>
  18#include <asm/gpio.h>
  19#include <asm/mach-imx/iomux-v3.h>
  20#include <asm/mach-imx/sata.h>
  21#include <mmc.h>
  22#include <fsl_esdhc_imx.h>
  23#include <asm/arch/crm_regs.h>
  24#include <asm/io.h>
  25#include <asm/arch/sys_proto.h>
  26#include <micrel.h>
  27#include <miiphy.h>
  28#include <netdev.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  38
  39#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40        PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43#define WDT_EN          IMX_GPIO_NR(5, 4)
  44#define WDT_TRG         IMX_GPIO_NR(3, 19)
  45
  46int dram_init(void)
  47{
  48        gd->ram_size = imx_ddr_size();
  49
  50        return 0;
  51}
  52
  53static iomux_v3_cfg_t const uart2_pads[] = {
  54        IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  55        IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  56};
  57
  58static iomux_v3_cfg_t const usdhc3_pads[] = {
  59        IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60        IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61        IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62        IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63        IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64        IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65};
  66
  67static iomux_v3_cfg_t const wdog_pads[] = {
  68        IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69        IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
  70};
  71
  72int mx6_rgmii_rework(struct phy_device *phydev)
  73{
  74        /*
  75         * Bug: Apparently uDoo does not works with Gigabit switches...
  76         * Limiting speed to 10/100Mbps, and setting master mode, seems to
  77         * be the only way to have a successfull PHY auto negotiation.
  78         * How to fix: Understand why Linux kernel do not have this issue.
  79         */
  80        phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  81
  82        /* control data pad skew - devaddr = 0x02, register = 0x04 */
  83        ksz9031_phy_extended_write(phydev, 0x02,
  84                                   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  85                                   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  86        /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  87        ksz9031_phy_extended_write(phydev, 0x02,
  88                                   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  89                                   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  90        /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  91        ksz9031_phy_extended_write(phydev, 0x02,
  92                                   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  93                                   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  94        /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  95        ksz9031_phy_extended_write(phydev, 0x02,
  96                                   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  97                                   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  98        return 0;
  99}
 100
 101static iomux_v3_cfg_t const enet_pads1[] = {
 102        IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103        IOMUX_PADS(PAD_ENET_MDC__ENET_MDC               | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 104        IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 105        IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 106        IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 107        IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 108        IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 109        IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 110        IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK        | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 111        IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 112        /* RGMII reset */
 113        IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23              | MUX_PAD_CTRL(NO_PAD_CTRL)),
 114        /* Ethernet power supply */
 115        IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31              | MUX_PAD_CTRL(NO_PAD_CTRL)),
 116        /* pin 32 - 1 - (MODE0) all */
 117        IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25            | MUX_PAD_CTRL(NO_PAD_CTRL)),
 118        /* pin 31 - 1 - (MODE1) all */
 119        IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27            | MUX_PAD_CTRL(NO_PAD_CTRL)),
 120        /* pin 28 - 1 - (MODE2) all */
 121        IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28            | MUX_PAD_CTRL(NO_PAD_CTRL)),
 122        /* pin 27 - 1 - (MODE3) all */
 123        IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29            | MUX_PAD_CTRL(NO_PAD_CTRL)),
 124        /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 125        IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 126};
 127
 128static iomux_v3_cfg_t const enet_pads2[] = {
 129        IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 130        IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 131        IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 132        IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 133        IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 134};
 135
 136static void setup_iomux_enet(void)
 137{
 138        SETUP_IOMUX_PADS(enet_pads1);
 139        udelay(20);
 140        gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
 141
 142        gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
 143
 144        gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 145        gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 146        gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 147        gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 148        gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 149        udelay(1000);
 150
 151        gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
 152
 153        /* Need 100ms delay to exit from reset. */
 154        udelay(1000 * 100);
 155
 156        gpio_free(IMX_GPIO_NR(6, 24));
 157        gpio_free(IMX_GPIO_NR(6, 25));
 158        gpio_free(IMX_GPIO_NR(6, 27));
 159        gpio_free(IMX_GPIO_NR(6, 28));
 160        gpio_free(IMX_GPIO_NR(6, 29));
 161
 162        SETUP_IOMUX_PADS(enet_pads2);
 163}
 164
 165static void setup_iomux_uart(void)
 166{
 167        SETUP_IOMUX_PADS(uart2_pads);
 168}
 169
 170static void setup_iomux_wdog(void)
 171{
 172        SETUP_IOMUX_PADS(wdog_pads);
 173        gpio_direction_output(WDT_TRG, 0);
 174        gpio_direction_output(WDT_EN, 1);
 175        gpio_direction_input(WDT_TRG);
 176}
 177
 178static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 179
 180int board_mmc_getcd(struct mmc *mmc)
 181{
 182        return 1; /* Always present */
 183}
 184
 185int board_eth_init(struct bd_info *bis)
 186{
 187        uint32_t base = IMX_FEC_BASE;
 188        struct mii_dev *bus = NULL;
 189        struct phy_device *phydev = NULL;
 190        int ret;
 191
 192        setup_iomux_enet();
 193
 194#ifdef CONFIG_FEC_MXC
 195        bus = fec_get_miibus(base, -1);
 196        if (!bus)
 197                return -EINVAL;
 198        /* scan phy 4,5,6,7 */
 199        phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 200
 201        if (!phydev) {
 202                ret = -EINVAL;
 203                goto free_bus;
 204        }
 205        printf("using phy at %d\n", phydev->addr);
 206        ret  = fec_probe(bis, -1, base, bus, phydev);
 207        if (ret)
 208                goto free_phydev;
 209#endif
 210        return 0;
 211
 212free_phydev:
 213        free(phydev);
 214free_bus:
 215        free(bus);
 216        return ret;
 217}
 218
 219int board_mmc_init(struct bd_info *bis)
 220{
 221        SETUP_IOMUX_PADS(usdhc3_pads);
 222        usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 223        usdhc_cfg.max_bus_width = 4;
 224
 225        return fsl_esdhc_initialize(bis, &usdhc_cfg);
 226}
 227
 228int board_early_init_f(void)
 229{
 230        setup_iomux_wdog();
 231        setup_iomux_uart();
 232
 233        return 0;
 234}
 235
 236int board_phy_config(struct phy_device *phydev)
 237{
 238        mx6_rgmii_rework(phydev);
 239        if (phydev->drv->config)
 240                phydev->drv->config(phydev);
 241
 242        return 0;
 243}
 244
 245int board_init(void)
 246{
 247        /* address of boot parameters */
 248        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 249
 250#ifdef CONFIG_SATA
 251        setup_sata();
 252#endif
 253        return 0;
 254}
 255
 256int board_late_init(void)
 257{
 258#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 259        if (is_cpu_type(MXC_CPU_MX6Q))
 260                env_set("board_rev", "MX6Q");
 261        else
 262                env_set("board_rev", "MX6DL");
 263#endif
 264        return 0;
 265}
 266
 267int checkboard(void)
 268{
 269        if (is_cpu_type(MXC_CPU_MX6Q))
 270                puts("Board: Udoo Quad\n");
 271        else
 272                puts("Board: Udoo DualLite\n");
 273
 274        return 0;
 275}
 276