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7#include <common.h>
8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
11#include <log.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mn-clock.h>
15
16#include "clk.h"
17
18#define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44};
45
46static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48};
49
50static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mn_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
54};
55
56static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mn_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
60};
61
62static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mn_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
66};
67
68static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
78static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
79 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
84#ifndef CONFIG_SPL_BUILD
85static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93#endif
94
95static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
98static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
99 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
100 "clk_ext4", "audio_pll2_out", };
101
102static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
103 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
104
105static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
106 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
107
108static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
109 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
110
111static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
112 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
113
114static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
115 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
116
117static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
118 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
119
120static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
121 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
122
123static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
124 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
125
126static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
127 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
128
129static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
130 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
131 "clk_ext3", "audio_pll2_out", };
132
133static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
134 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
135 "clk_ext3", "audio_pll2_out", };
136
137static ulong imx8mn_clk_get_rate(struct clk *clk)
138{
139 struct clk *c;
140 int ret;
141
142 debug("%s(#%lu)\n", __func__, clk->id);
143
144 ret = clk_get_by_id(clk->id, &c);
145 if (ret)
146 return ret;
147
148 return clk_get_rate(c);
149}
150
151static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
152{
153 struct clk *c;
154 int ret;
155
156 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
157
158 ret = clk_get_by_id(clk->id, &c);
159 if (ret)
160 return ret;
161
162 return clk_set_rate(c, rate);
163}
164
165static int __imx8mn_clk_enable(struct clk *clk, bool enable)
166{
167 struct clk *c;
168 int ret;
169
170 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
171
172 ret = clk_get_by_id(clk->id, &c);
173 if (ret)
174 return ret;
175
176 if (enable)
177 ret = clk_enable(c);
178 else
179 ret = clk_disable(c);
180
181 return ret;
182}
183
184static int imx8mn_clk_disable(struct clk *clk)
185{
186 return __imx8mn_clk_enable(clk, 0);
187}
188
189static int imx8mn_clk_enable(struct clk *clk)
190{
191 return __imx8mn_clk_enable(clk, 1);
192}
193
194static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
195{
196 struct clk *c, *cp;
197 int ret;
198
199 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
200
201 ret = clk_get_by_id(clk->id, &c);
202 if (ret)
203 return ret;
204
205 ret = clk_get_by_id(parent->id, &cp);
206 if (ret)
207 return ret;
208
209 ret = clk_set_parent(c, cp);
210 c->dev->parent = cp->dev;
211
212 return ret;
213}
214
215static struct clk_ops imx8mn_clk_ops = {
216 .set_rate = imx8mn_clk_set_rate,
217 .get_rate = imx8mn_clk_get_rate,
218 .enable = imx8mn_clk_enable,
219 .disable = imx8mn_clk_disable,
220 .set_parent = imx8mn_clk_set_parent,
221};
222
223static int imx8mn_clk_probe(struct udevice *dev)
224{
225 void __iomem *base;
226
227 base = (void *)ANATOP_BASE_ADDR;
228
229 clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
230 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
231 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
232 clk_dm(IMX8MN_ARM_PLL_REF_SEL,
233 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
234 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
235 clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
236 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
237 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
238 clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
239 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
240 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
241 clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
242 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
243 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
244
245 clk_dm(IMX8MN_DRAM_PLL,
246 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
247 base + 0x50, &imx8mn_dram_pll));
248 clk_dm(IMX8MN_ARM_PLL,
249 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
250 base + 0x84, &imx8mn_arm_pll));
251 clk_dm(IMX8MN_SYS_PLL1,
252 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
253 base + 0x94, &imx8mn_sys_pll));
254 clk_dm(IMX8MN_SYS_PLL2,
255 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
256 base + 0x104, &imx8mn_sys_pll));
257 clk_dm(IMX8MN_SYS_PLL3,
258 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
259 base + 0x114, &imx8mn_sys_pll));
260
261
262 clk_dm(IMX8MN_DRAM_PLL_BYPASS,
263 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
264 dram_pll_bypass_sels,
265 ARRAY_SIZE(dram_pll_bypass_sels),
266 CLK_SET_RATE_PARENT));
267 clk_dm(IMX8MN_ARM_PLL_BYPASS,
268 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
269 arm_pll_bypass_sels,
270 ARRAY_SIZE(arm_pll_bypass_sels),
271 CLK_SET_RATE_PARENT));
272 clk_dm(IMX8MN_SYS_PLL1_BYPASS,
273 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
274 sys_pll1_bypass_sels,
275 ARRAY_SIZE(sys_pll1_bypass_sels),
276 CLK_SET_RATE_PARENT));
277 clk_dm(IMX8MN_SYS_PLL2_BYPASS,
278 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
279 sys_pll2_bypass_sels,
280 ARRAY_SIZE(sys_pll2_bypass_sels),
281 CLK_SET_RATE_PARENT));
282 clk_dm(IMX8MN_SYS_PLL3_BYPASS,
283 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
284 sys_pll3_bypass_sels,
285 ARRAY_SIZE(sys_pll3_bypass_sels),
286 CLK_SET_RATE_PARENT));
287
288
289 clk_dm(IMX8MN_DRAM_PLL_OUT,
290 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
291 base + 0x50, 13));
292 clk_dm(IMX8MN_ARM_PLL_OUT,
293 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
294 base + 0x84, 11));
295 clk_dm(IMX8MN_SYS_PLL1_OUT,
296 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
297 base + 0x94, 11));
298 clk_dm(IMX8MN_SYS_PLL2_OUT,
299 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
300 base + 0x104, 11));
301 clk_dm(IMX8MN_SYS_PLL3_OUT,
302 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
303 base + 0x114, 11));
304
305
306 clk_dm(IMX8MN_SYS_PLL1_40M,
307 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
308 clk_dm(IMX8MN_SYS_PLL1_80M,
309 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
310 clk_dm(IMX8MN_SYS_PLL1_100M,
311 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
312 clk_dm(IMX8MN_SYS_PLL1_133M,
313 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
314 clk_dm(IMX8MN_SYS_PLL1_160M,
315 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
316 clk_dm(IMX8MN_SYS_PLL1_200M,
317 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
318 clk_dm(IMX8MN_SYS_PLL1_266M,
319 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
320 clk_dm(IMX8MN_SYS_PLL1_400M,
321 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
322 clk_dm(IMX8MN_SYS_PLL1_800M,
323 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
324
325 clk_dm(IMX8MN_SYS_PLL2_50M,
326 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
327 clk_dm(IMX8MN_SYS_PLL2_100M,
328 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
329 clk_dm(IMX8MN_SYS_PLL2_125M,
330 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
331 clk_dm(IMX8MN_SYS_PLL2_166M,
332 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
333 clk_dm(IMX8MN_SYS_PLL2_200M,
334 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
335 clk_dm(IMX8MN_SYS_PLL2_250M,
336 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
337 clk_dm(IMX8MN_SYS_PLL2_333M,
338 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
339 clk_dm(IMX8MN_SYS_PLL2_500M,
340 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
341 clk_dm(IMX8MN_SYS_PLL2_1000M,
342 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
343
344 base = dev_read_addr_ptr(dev);
345 if (!base)
346 return -EINVAL;
347
348 clk_dm(IMX8MN_CLK_A53_SRC,
349 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
350 imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
351 clk_dm(IMX8MN_CLK_A53_CG,
352 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
353 clk_dm(IMX8MN_CLK_A53_DIV,
354 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
355 base + 0x8000, 0, 3));
356
357 clk_dm(IMX8MN_CLK_AHB,
358 imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
359 base + 0x9000));
360 clk_dm(IMX8MN_CLK_IPG_ROOT,
361 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
362
363 clk_dm(IMX8MN_CLK_ENET_AXI,
364 imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
365 base + 0x8880));
366 clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
367 imx8m_clk_composite_critical("nand_usdhc_bus",
368 imx8mn_nand_usdhc_sels,
369 base + 0x8900));
370 clk_dm(IMX8MN_CLK_USB_BUS,
371 imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
372
373
374 clk_dm(IMX8MN_CLK_USDHC1,
375 imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
376 base + 0xac00));
377 clk_dm(IMX8MN_CLK_USDHC2,
378 imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
379 base + 0xac80));
380 clk_dm(IMX8MN_CLK_I2C1,
381 imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
382 clk_dm(IMX8MN_CLK_I2C2,
383 imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
384 clk_dm(IMX8MN_CLK_I2C3,
385 imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
386 clk_dm(IMX8MN_CLK_I2C4,
387 imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
388 clk_dm(IMX8MN_CLK_WDOG,
389 imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
390 clk_dm(IMX8MN_CLK_USDHC3,
391 imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
392 base + 0xbc80));
393 clk_dm(IMX8MN_CLK_QSPI,
394 imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
395 clk_dm(IMX8MN_CLK_USB_CORE_REF,
396 imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
397 clk_dm(IMX8MN_CLK_USB_PHY_REF,
398 imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
399
400 clk_dm(IMX8MN_CLK_I2C1_ROOT,
401 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
402 clk_dm(IMX8MN_CLK_I2C2_ROOT,
403 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
404 clk_dm(IMX8MN_CLK_I2C3_ROOT,
405 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
406 clk_dm(IMX8MN_CLK_I2C4_ROOT,
407 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
408 clk_dm(IMX8MN_CLK_OCOTP_ROOT,
409 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
410 clk_dm(IMX8MN_CLK_USDHC1_ROOT,
411 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
412 clk_dm(IMX8MN_CLK_USDHC2_ROOT,
413 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
414 clk_dm(IMX8MN_CLK_WDOG1_ROOT,
415 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
416 clk_dm(IMX8MN_CLK_WDOG2_ROOT,
417 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
418 clk_dm(IMX8MN_CLK_WDOG3_ROOT,
419 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
420 clk_dm(IMX8MN_CLK_USDHC3_ROOT,
421 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
422 clk_dm(IMX8MN_CLK_QSPI_ROOT,
423 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
424 clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
425 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
426
427
428#ifndef CONFIG_SPL_BUILD
429 clk_dm(IMX8MN_CLK_ENET_REF,
430 imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
431 base + 0xa980));
432 clk_dm(IMX8MN_CLK_ENET_TIMER,
433 imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
434 base + 0xaa00));
435 clk_dm(IMX8MN_CLK_ENET_PHY_REF,
436 imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
437 base + 0xaa80));
438 clk_dm(IMX8MN_CLK_ENET1_ROOT,
439 imx_clk_gate4("enet1_root_clk", "enet_axi",
440 base + 0x40a0, 0));
441#endif
442
443 return 0;
444}
445
446static const struct udevice_id imx8mn_clk_ids[] = {
447 { .compatible = "fsl,imx8mn-ccm" },
448 { },
449};
450
451U_BOOT_DRIVER(imx8mn_clk) = {
452 .name = "clk_imx8mn",
453 .id = UCLASS_CLK,
454 .of_match = imx8mn_clk_ids,
455 .ops = &imx8mn_clk_ops,
456 .probe = imx8mn_clk_probe,
457 .flags = DM_FLAG_PRE_RELOC,
458};
459
