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7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <dt-structs.h>
11#include <errno.h>
12#include <log.h>
13#include <malloc.h>
14#include <mapmem.h>
15#include <syscon.h>
16#include <bitfield.h>
17#include <asm/io.h>
18#include <asm/arch-rockchip/clock.h>
19#include <asm/arch-rockchip/cru.h>
20#include <asm/arch-rockchip/hardware.h>
21#include <dm/lists.h>
22#include <dt-bindings/clock/rk3399-cru.h>
23#include <linux/bitops.h>
24#include <linux/delay.h>
25
26#if CONFIG_IS_ENABLED(OF_PLATDATA)
27struct rk3399_clk_plat {
28 struct dtd_rockchip_rk3399_cru dtd;
29};
30
31struct rk3399_pmuclk_plat {
32 struct dtd_rockchip_rk3399_pmucru dtd;
33};
34#endif
35
36struct pll_div {
37 u32 refdiv;
38 u32 fbdiv;
39 u32 postdiv1;
40 u32 postdiv2;
41 u32 frac;
42};
43
44#define RATE_TO_DIV(input_rate, output_rate) \
45 ((input_rate) / (output_rate) - 1)
46#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
47
48#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
49 .refdiv = _refdiv,\
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
52
53#if defined(CONFIG_SPL_BUILD)
54static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
55static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
56#else
57static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
58#endif
59
60static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
61static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
62
63static const struct pll_div *apll_l_cfgs[] = {
64 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
65 [APLL_L_600_MHZ] = &apll_l_600_cfg,
66};
67
68static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
69static const struct pll_div *apll_b_cfgs[] = {
70 [APLL_B_600_MHZ] = &apll_b_600_cfg,
71};
72
73enum {
74
75 PLL_FBDIV_MASK = 0xfff,
76 PLL_FBDIV_SHIFT = 0,
77
78
79 PLL_POSTDIV2_SHIFT = 12,
80 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
81 PLL_POSTDIV1_SHIFT = 8,
82 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
83 PLL_REFDIV_MASK = 0x3f,
84 PLL_REFDIV_SHIFT = 0,
85
86
87 PLL_LOCK_STATUS_SHIFT = 31,
88 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
89 PLL_FRACDIV_MASK = 0xffffff,
90 PLL_FRACDIV_SHIFT = 0,
91
92
93 PLL_MODE_SHIFT = 8,
94 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
95 PLL_MODE_SLOW = 0,
96 PLL_MODE_NORM,
97 PLL_MODE_DEEP,
98 PLL_DSMPD_SHIFT = 3,
99 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
100 PLL_INTEGER_MODE = 1,
101
102
103 PMU_PCLK_DIV_CON_MASK = 0x1f,
104 PMU_PCLK_DIV_CON_SHIFT = 0,
105
106
107 SPI3_PLL_SEL_SHIFT = 7,
108 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
109 SPI3_PLL_SEL_24M = 0,
110 SPI3_PLL_SEL_PPLL = 1,
111 SPI3_DIV_CON_SHIFT = 0x0,
112 SPI3_DIV_CON_MASK = 0x7f,
113
114
115 I2C_DIV_CON_MASK = 0x7f,
116 CLK_I2C8_DIV_CON_SHIFT = 8,
117 CLK_I2C0_DIV_CON_SHIFT = 0,
118
119
120 CLK_I2C4_DIV_CON_SHIFT = 0,
121
122
123 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
124 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
125 CLK_CORE_L_PLL_SEL_SHIFT = 6,
126 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
127 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
128 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
129 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
130 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
131 CLK_CORE_L_DIV_MASK = 0x1f,
132 CLK_CORE_L_DIV_SHIFT = 0,
133
134
135 PCLK_DBG_L_DIV_SHIFT = 0x8,
136 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
137 ATCLK_CORE_L_DIV_SHIFT = 0,
138 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
139
140
141 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
142 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
143 CLK_CORE_B_PLL_SEL_SHIFT = 6,
144 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
145 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
146 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
147 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
148 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
149 CLK_CORE_B_DIV_MASK = 0x1f,
150 CLK_CORE_B_DIV_SHIFT = 0,
151
152
153 PCLK_DBG_B_DIV_SHIFT = 0x8,
154 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
155 ATCLK_CORE_B_DIV_SHIFT = 0,
156 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
157
158
159 PCLK_PERIHP_DIV_CON_SHIFT = 12,
160 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
161 HCLK_PERIHP_DIV_CON_SHIFT = 8,
162 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
163 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
164 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
165 ACLK_PERIHP_PLL_SEL_CPLL = 0,
166 ACLK_PERIHP_PLL_SEL_GPLL = 1,
167 ACLK_PERIHP_DIV_CON_SHIFT = 0,
168 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
169
170
171 ACLK_EMMC_PLL_SEL_SHIFT = 7,
172 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
173 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
174 ACLK_EMMC_DIV_CON_SHIFT = 0,
175 ACLK_EMMC_DIV_CON_MASK = 0x1f,
176
177
178 CLK_EMMC_PLL_SHIFT = 8,
179 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
180 CLK_EMMC_PLL_SEL_GPLL = 0x1,
181 CLK_EMMC_PLL_SEL_24M = 0x5,
182 CLK_EMMC_DIV_CON_SHIFT = 0,
183 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
184
185
186 PCLK_PERILP0_DIV_CON_SHIFT = 12,
187 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
188 HCLK_PERILP0_DIV_CON_SHIFT = 8,
189 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
190 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
191 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
192 ACLK_PERILP0_PLL_SEL_CPLL = 0,
193 ACLK_PERILP0_PLL_SEL_GPLL = 1,
194 ACLK_PERILP0_DIV_CON_SHIFT = 0,
195 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
196
197
198 PCLK_PERILP1_DIV_CON_SHIFT = 8,
199 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
200 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
201 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
202 HCLK_PERILP1_PLL_SEL_CPLL = 0,
203 HCLK_PERILP1_PLL_SEL_GPLL = 1,
204 HCLK_PERILP1_DIV_CON_SHIFT = 0,
205 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
206
207
208 CLK_SARADC_DIV_CON_SHIFT = 8,
209 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
210 CLK_SARADC_DIV_CON_WIDTH = 8,
211
212
213 CLK_TSADC_SEL_X24M = 0x0,
214 CLK_TSADC_SEL_SHIFT = 15,
215 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
216 CLK_TSADC_DIV_CON_SHIFT = 0,
217 CLK_TSADC_DIV_CON_MASK = 0x3ff,
218
219
220 ACLK_VOP_PLL_SEL_SHIFT = 6,
221 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
222 ACLK_VOP_PLL_SEL_CPLL = 0x1,
223 ACLK_VOP_DIV_CON_SHIFT = 0,
224 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
225
226
227 DCLK_VOP_DCLK_SEL_SHIFT = 11,
228 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
229 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
230 DCLK_VOP_PLL_SEL_SHIFT = 8,
231 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
232 DCLK_VOP_PLL_SEL_VPLL = 0,
233 DCLK_VOP_DIV_CON_MASK = 0xff,
234 DCLK_VOP_DIV_CON_SHIFT = 0,
235
236
237 CLK_SPI_PLL_SEL_WIDTH = 1,
238 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
239 CLK_SPI_PLL_SEL_CPLL = 0,
240 CLK_SPI_PLL_SEL_GPLL = 1,
241 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
242 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
243
244 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
245 CLK_SPI5_PLL_SEL_SHIFT = 15,
246
247
248 CLK_SPI1_PLL_SEL_SHIFT = 15,
249 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
250 CLK_SPI0_PLL_SEL_SHIFT = 7,
251 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
252
253
254 CLK_SPI4_PLL_SEL_SHIFT = 15,
255 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
256 CLK_SPI2_PLL_SEL_SHIFT = 7,
257 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
258
259
260 CLK_I2C_PLL_SEL_MASK = 1,
261 CLK_I2C_PLL_SEL_CPLL = 0,
262 CLK_I2C_PLL_SEL_GPLL = 1,
263 CLK_I2C5_PLL_SEL_SHIFT = 15,
264 CLK_I2C5_DIV_CON_SHIFT = 8,
265 CLK_I2C1_PLL_SEL_SHIFT = 7,
266 CLK_I2C1_DIV_CON_SHIFT = 0,
267
268
269 CLK_I2C6_PLL_SEL_SHIFT = 15,
270 CLK_I2C6_DIV_CON_SHIFT = 8,
271 CLK_I2C2_PLL_SEL_SHIFT = 7,
272 CLK_I2C2_DIV_CON_SHIFT = 0,
273
274
275 CLK_I2C7_PLL_SEL_SHIFT = 15,
276 CLK_I2C7_DIV_CON_SHIFT = 8,
277 CLK_I2C3_PLL_SEL_SHIFT = 7,
278 CLK_I2C3_DIV_CON_SHIFT = 0,
279
280
281 RESETN_DDR0_REQ_SHIFT = 8,
282 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
283 RESETN_DDRPHY0_REQ_SHIFT = 9,
284 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
285 RESETN_DDR1_REQ_SHIFT = 12,
286 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
287 RESETN_DDRPHY1_REQ_SHIFT = 13,
288 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
289};
290
291#define VCO_MAX_KHZ (3200 * (MHz / KHz))
292#define VCO_MIN_KHZ (800 * (MHz / KHz))
293#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
294#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
295
296
297
298
299
300#define PLL_DIV_MIN 16
301#define PLL_DIV_MAX 3200
302
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314
315
316
317
318static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
319{
320
321 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
322 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
323
324 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
325 "postdiv2=%d, vco=%u khz, output=%u khz\n",
326 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
327 div->postdiv2, vco_khz, output_khz);
328 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
329 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
330 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
331
332
333
334
335
336 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
337 PLL_MODE_SLOW << PLL_MODE_SHIFT);
338
339
340 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
341 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
342
343 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
344 div->fbdiv << PLL_FBDIV_SHIFT);
345 rk_clrsetreg(&pll_con[1],
346 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
347 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
348 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
349 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
350 (div->refdiv << PLL_REFDIV_SHIFT));
351
352
353 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
354 udelay(1);
355
356
357 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
358 PLL_MODE_NORM << PLL_MODE_SHIFT);
359}
360
361static int pll_para_config(u32 freq_hz, struct pll_div *div)
362{
363 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
364 u32 postdiv1, postdiv2 = 1;
365 u32 fref_khz;
366 u32 diff_khz, best_diff_khz;
367 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
368 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
369 u32 vco_khz;
370 u32 freq_khz = freq_hz / KHz;
371
372 if (!freq_hz) {
373 printf("%s: the frequency can't be 0 Hz\n", __func__);
374 return -1;
375 }
376
377 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
378 if (postdiv1 > max_postdiv1) {
379 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
380 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
381 }
382
383 vco_khz = freq_khz * postdiv1 * postdiv2;
384
385 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
386 postdiv2 > max_postdiv2) {
387 printf("%s: Cannot find out a supported VCO"
388 " for Frequency (%uHz).\n", __func__, freq_hz);
389 return -1;
390 }
391
392 div->postdiv1 = postdiv1;
393 div->postdiv2 = postdiv2;
394
395 best_diff_khz = vco_khz;
396 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
397 fref_khz = ref_khz / refdiv;
398
399 fbdiv = vco_khz / fref_khz;
400 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
401 continue;
402 diff_khz = vco_khz - fbdiv * fref_khz;
403 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
404 fbdiv++;
405 diff_khz = fref_khz - diff_khz;
406 }
407
408 if (diff_khz >= best_diff_khz)
409 continue;
410
411 best_diff_khz = diff_khz;
412 div->refdiv = refdiv;
413 div->fbdiv = fbdiv;
414 }
415
416 if (best_diff_khz > 4 * (MHz / KHz)) {
417 printf("%s: Failed to match output frequency %u, "
418 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
419 best_diff_khz * KHz);
420 return -1;
421 }
422 return 0;
423}
424
425void rk3399_configure_cpu_l(struct rockchip_cru *cru,
426 enum apll_l_frequencies apll_l_freq)
427{
428 u32 aclkm_div;
429 u32 pclk_dbg_div;
430 u32 atclk_div;
431
432
433 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
434
435 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
436 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
437 aclkm_div < 0x1f);
438
439 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
440 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
441 pclk_dbg_div < 0x1f);
442
443 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
444 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
445 atclk_div < 0x1f);
446
447 rk_clrsetreg(&cru->clksel_con[0],
448 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
449 CLK_CORE_L_DIV_MASK,
450 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
451 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
452 0 << CLK_CORE_L_DIV_SHIFT);
453
454 rk_clrsetreg(&cru->clksel_con[1],
455 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
456 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
457 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
458}
459
460void rk3399_configure_cpu_b(struct rockchip_cru *cru,
461 enum apll_b_frequencies apll_b_freq)
462{
463 u32 aclkm_div;
464 u32 pclk_dbg_div;
465 u32 atclk_div;
466
467
468 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
469
470 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
471 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
472 aclkm_div < 0x1f);
473
474 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
475 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
476 pclk_dbg_div < 0x1f);
477
478 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
479 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
480 atclk_div < 0x1f);
481
482 rk_clrsetreg(&cru->clksel_con[2],
483 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
484 CLK_CORE_B_DIV_MASK,
485 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
486 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
487 0 << CLK_CORE_B_DIV_SHIFT);
488
489 rk_clrsetreg(&cru->clksel_con[3],
490 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
491 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
492 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
493}
494
495#define I2C_CLK_REG_MASK(bus) \
496 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
497 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
498
499#define I2C_CLK_REG_VALUE(bus, clk_div) \
500 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
501 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
502
503#define I2C_CLK_DIV_VALUE(con, bus) \
504 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
505
506#define I2C_PMUCLK_REG_MASK(bus) \
507 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
508
509#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
510 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
511
512static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
513{
514 u32 div, con;
515
516 switch (clk_id) {
517 case SCLK_I2C1:
518 con = readl(&cru->clksel_con[61]);
519 div = I2C_CLK_DIV_VALUE(con, 1);
520 break;
521 case SCLK_I2C2:
522 con = readl(&cru->clksel_con[62]);
523 div = I2C_CLK_DIV_VALUE(con, 2);
524 break;
525 case SCLK_I2C3:
526 con = readl(&cru->clksel_con[63]);
527 div = I2C_CLK_DIV_VALUE(con, 3);
528 break;
529 case SCLK_I2C5:
530 con = readl(&cru->clksel_con[61]);
531 div = I2C_CLK_DIV_VALUE(con, 5);
532 break;
533 case SCLK_I2C6:
534 con = readl(&cru->clksel_con[62]);
535 div = I2C_CLK_DIV_VALUE(con, 6);
536 break;
537 case SCLK_I2C7:
538 con = readl(&cru->clksel_con[63]);
539 div = I2C_CLK_DIV_VALUE(con, 7);
540 break;
541 default:
542 printf("do not support this i2c bus\n");
543 return -EINVAL;
544 }
545
546 return DIV_TO_RATE(GPLL_HZ, div);
547}
548
549static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
550{
551 int src_clk_div;
552
553
554 src_clk_div = GPLL_HZ / hz;
555 assert(src_clk_div - 1 < 127);
556
557 switch (clk_id) {
558 case SCLK_I2C1:
559 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
560 I2C_CLK_REG_VALUE(1, src_clk_div));
561 break;
562 case SCLK_I2C2:
563 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
564 I2C_CLK_REG_VALUE(2, src_clk_div));
565 break;
566 case SCLK_I2C3:
567 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
568 I2C_CLK_REG_VALUE(3, src_clk_div));
569 break;
570 case SCLK_I2C5:
571 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
572 I2C_CLK_REG_VALUE(5, src_clk_div));
573 break;
574 case SCLK_I2C6:
575 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
576 I2C_CLK_REG_VALUE(6, src_clk_div));
577 break;
578 case SCLK_I2C7:
579 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
580 I2C_CLK_REG_VALUE(7, src_clk_div));
581 break;
582 default:
583 printf("do not support this i2c bus\n");
584 return -EINVAL;
585 }
586
587 return rk3399_i2c_get_clk(cru, clk_id);
588}
589
590
591
592
593
594
595
596struct spi_clkreg {
597 u8 reg;
598 u8 div_shift;
599 u8 sel_shift;
600};
601
602
603
604
605
606
607
608static const struct spi_clkreg spi_clkregs[] = {
609 [0] = { .reg = 59,
610 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
611 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
612 [1] = { .reg = 59,
613 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
614 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
615 [2] = { .reg = 60,
616 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
617 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
618 [3] = { .reg = 60,
619 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
620 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
621 [4] = { .reg = 58,
622 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
623 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
624};
625
626static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
627{
628 const struct spi_clkreg *spiclk = NULL;
629 u32 div, val;
630
631 switch (clk_id) {
632 case SCLK_SPI0 ... SCLK_SPI5:
633 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
634 break;
635
636 default:
637 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
638 return -EINVAL;
639 }
640
641 val = readl(&cru->clksel_con[spiclk->reg]);
642 div = bitfield_extract(val, spiclk->div_shift,
643 CLK_SPI_PLL_DIV_CON_WIDTH);
644
645 return DIV_TO_RATE(GPLL_HZ, div);
646}
647
648static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
649{
650 const struct spi_clkreg *spiclk = NULL;
651 int src_clk_div;
652
653 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
654 assert(src_clk_div < 128);
655
656 switch (clk_id) {
657 case SCLK_SPI1 ... SCLK_SPI5:
658 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
659 break;
660
661 default:
662 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
663 return -EINVAL;
664 }
665
666 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
667 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
668 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
669 ((src_clk_div << spiclk->div_shift) |
670 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
671
672 return rk3399_spi_get_clk(cru, clk_id);
673}
674
675static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
676{
677 struct pll_div vpll_config = {0};
678 int aclk_vop = 198 * MHz;
679 void *aclkreg_addr, *dclkreg_addr;
680 u32 div;
681
682 switch (clk_id) {
683 case DCLK_VOP0:
684 aclkreg_addr = &cru->clksel_con[47];
685 dclkreg_addr = &cru->clksel_con[49];
686 break;
687 case DCLK_VOP1:
688 aclkreg_addr = &cru->clksel_con[48];
689 dclkreg_addr = &cru->clksel_con[50];
690 break;
691 default:
692 return -EINVAL;
693 }
694
695 div = CPLL_HZ / aclk_vop;
696 assert(div - 1 < 32);
697
698 rk_clrsetreg(aclkreg_addr,
699 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
700 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
701 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
702
703
704 if (pll_para_config(hz, &vpll_config))
705 return -1;
706
707 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
708
709 rk_clrsetreg(dclkreg_addr,
710 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
711 DCLK_VOP_DIV_CON_MASK,
712 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
713 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
714 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
715
716 return hz;
717}
718
719static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
720{
721 u32 div, con;
722
723 switch (clk_id) {
724 case HCLK_SDMMC:
725 case SCLK_SDMMC:
726 con = readl(&cru->clksel_con[16]);
727
728 div = 2;
729 break;
730 case SCLK_EMMC:
731 con = readl(&cru->clksel_con[22]);
732 div = 1;
733 break;
734 default:
735 return -EINVAL;
736 }
737
738 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
739 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
740 == CLK_EMMC_PLL_SEL_24M)
741 return DIV_TO_RATE(OSC_HZ, div);
742 else
743 return DIV_TO_RATE(GPLL_HZ, div);
744}
745
746static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
747 ulong clk_id, ulong set_rate)
748{
749 int src_clk_div;
750 int aclk_emmc = 198 * MHz;
751
752 switch (clk_id) {
753 case HCLK_SDMMC:
754 case SCLK_SDMMC:
755
756
757 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
758
759 if (src_clk_div > 128) {
760
761 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
762 assert(src_clk_div - 1 < 128);
763 rk_clrsetreg(&cru->clksel_con[16],
764 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
765 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
766 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
767 } else {
768 rk_clrsetreg(&cru->clksel_con[16],
769 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
770 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
771 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
772 }
773 break;
774 case SCLK_EMMC:
775
776 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
777 assert(src_clk_div - 1 < 32);
778
779 rk_clrsetreg(&cru->clksel_con[21],
780 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
781 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
782 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
783
784
785 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
786 assert(src_clk_div - 1 < 128);
787
788 rk_clrsetreg(&cru->clksel_con[22],
789 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
790 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
791 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
792 break;
793 default:
794 return -EINVAL;
795 }
796 return rk3399_mmc_get_clk(cru, clk_id);
797}
798
799static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
800{
801 ulong ret;
802
803
804
805
806
807 if (readl(&cru->clksel_con[19]) & BIT(4)) {
808
809 ret = rate;
810 } else {
811
812
813
814
815
816 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
817 ret = 0;
818 }
819
820 return ret;
821}
822
823#define PMUSGRF_DDR_RGN_CON16 0xff330040
824static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
825 ulong set_rate)
826{
827 struct pll_div dpll_cfg;
828
829
830 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
831
832
833 switch (set_rate) {
834 case 50 * MHz:
835 dpll_cfg = (struct pll_div)
836 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
837 break;
838 case 200 * MHz:
839 dpll_cfg = (struct pll_div)
840 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
841 break;
842 case 300 * MHz:
843 dpll_cfg = (struct pll_div)
844 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
845 break;
846 case 400 * MHz:
847 dpll_cfg = (struct pll_div)
848 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
849 break;
850 case 666 * MHz:
851 dpll_cfg = (struct pll_div)
852 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
853 break;
854 case 800 * MHz:
855 dpll_cfg = (struct pll_div)
856 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
857 break;
858 case 933 * MHz:
859 dpll_cfg = (struct pll_div)
860 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
861 break;
862 default:
863 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
864 }
865 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
866
867 return set_rate;
868}
869
870static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
871{
872 u32 div, val;
873
874 val = readl(&cru->clksel_con[26]);
875 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
876 CLK_SARADC_DIV_CON_WIDTH);
877
878 return DIV_TO_RATE(OSC_HZ, div);
879}
880
881static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
882{
883 int src_clk_div;
884
885 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
886 assert(src_clk_div < 128);
887
888 rk_clrsetreg(&cru->clksel_con[26],
889 CLK_SARADC_DIV_CON_MASK,
890 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
891
892 return rk3399_saradc_get_clk(cru);
893}
894
895static ulong rk3399_clk_get_rate(struct clk *clk)
896{
897 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
898 ulong rate = 0;
899
900 switch (clk->id) {
901 case 0 ... 63:
902 return 0;
903 case HCLK_SDMMC:
904 case SCLK_SDMMC:
905 case SCLK_EMMC:
906 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
907 break;
908 case SCLK_I2C1:
909 case SCLK_I2C2:
910 case SCLK_I2C3:
911 case SCLK_I2C5:
912 case SCLK_I2C6:
913 case SCLK_I2C7:
914 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
915 break;
916 case SCLK_SPI0...SCLK_SPI5:
917 rate = rk3399_spi_get_clk(priv->cru, clk->id);
918 break;
919 case SCLK_UART0:
920 case SCLK_UART1:
921 case SCLK_UART2:
922 case SCLK_UART3:
923 return 24000000;
924 case PCLK_HDMI_CTRL:
925 break;
926 case DCLK_VOP0:
927 case DCLK_VOP1:
928 break;
929 case PCLK_EFUSE1024NS:
930 break;
931 case SCLK_SARADC:
932 rate = rk3399_saradc_get_clk(priv->cru);
933 break;
934 case ACLK_VIO:
935 case ACLK_HDCP:
936 case ACLK_GIC_PRE:
937 case PCLK_DDR:
938 break;
939 default:
940 log_debug("Unknown clock %lu\n", clk->id);
941 return -ENOENT;
942 }
943
944 return rate;
945}
946
947static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
948{
949 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
950 ulong ret = 0;
951
952 switch (clk->id) {
953 case 0 ... 63:
954 return 0;
955
956 case ACLK_PERIHP:
957 case HCLK_PERIHP:
958 case PCLK_PERIHP:
959 return 0;
960
961 case ACLK_PERILP0:
962 case HCLK_PERILP0:
963 case PCLK_PERILP0:
964 return 0;
965
966 case ACLK_CCI:
967 return 0;
968
969 case HCLK_PERILP1:
970 case PCLK_PERILP1:
971 return 0;
972
973 case HCLK_SDMMC:
974 case SCLK_SDMMC:
975 case SCLK_EMMC:
976 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
977 break;
978 case SCLK_MAC:
979 ret = rk3399_gmac_set_clk(priv->cru, rate);
980 break;
981 case SCLK_I2C1:
982 case SCLK_I2C2:
983 case SCLK_I2C3:
984 case SCLK_I2C5:
985 case SCLK_I2C6:
986 case SCLK_I2C7:
987 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
988 break;
989 case SCLK_SPI0...SCLK_SPI5:
990 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
991 break;
992 case PCLK_HDMI_CTRL:
993 case PCLK_VIO_GRF:
994
995 break;
996 case DCLK_VOP0:
997 case DCLK_VOP1:
998 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
999 break;
1000 case ACLK_VOP1:
1001 case HCLK_VOP1:
1002 case HCLK_SD:
1003 case SCLK_UPHY0_TCPDCORE:
1004 case SCLK_UPHY1_TCPDCORE:
1005
1006
1007
1008
1009 return 0;
1010 case SCLK_DDRCLK:
1011 ret = rk3399_ddr_set_clk(priv->cru, rate);
1012 break;
1013 case PCLK_EFUSE1024NS:
1014 break;
1015 case SCLK_SARADC:
1016 ret = rk3399_saradc_set_clk(priv->cru, rate);
1017 break;
1018 case ACLK_VIO:
1019 case ACLK_HDCP:
1020 case ACLK_GIC_PRE:
1021 case PCLK_DDR:
1022 return 0;
1023 default:
1024 log_debug("Unknown clock %lu\n", clk->id);
1025 return -ENOENT;
1026 }
1027
1028 return ret;
1029}
1030
1031static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1032 struct clk *parent)
1033{
1034 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1035 const char *clock_output_name;
1036 int ret;
1037
1038
1039
1040
1041
1042 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1043 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1044 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1045 return 0;
1046 }
1047
1048
1049
1050
1051
1052 ret = dev_read_string_index(parent->dev, "clock-output-names",
1053 parent->id, &clock_output_name);
1054 if (ret < 0)
1055 return -ENODATA;
1056
1057
1058 if (!strcmp(clock_output_name, "clkin_gmac")) {
1059 debug("%s: switching RGMII to CLKIN\n", __func__);
1060 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1061 return 0;
1062 }
1063
1064 return -EINVAL;
1065}
1066
1067static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1068 struct clk *parent)
1069{
1070 switch (clk->id) {
1071 case SCLK_RMII_SRC:
1072 return rk3399_gmac_set_parent(clk, parent);
1073 }
1074
1075 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1076 return -ENOENT;
1077}
1078
1079static int rk3399_clk_enable(struct clk *clk)
1080{
1081 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1082
1083 switch (clk->id) {
1084 case SCLK_MAC:
1085 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1086 break;
1087 case SCLK_MAC_RX:
1088 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1089 break;
1090 case SCLK_MAC_TX:
1091 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1092 break;
1093 case SCLK_MACREF:
1094 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1095 break;
1096 case SCLK_MACREF_OUT:
1097 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1098 break;
1099 case SCLK_USB2PHY0_REF:
1100 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1101 break;
1102 case SCLK_USB2PHY1_REF:
1103 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1104 break;
1105 case ACLK_GMAC:
1106 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1107 break;
1108 case PCLK_GMAC:
1109 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1110 break;
1111 case SCLK_USB3OTG0_REF:
1112 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1113 break;
1114 case SCLK_USB3OTG1_REF:
1115 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1116 break;
1117 case SCLK_USB3OTG0_SUSPEND:
1118 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1119 break;
1120 case SCLK_USB3OTG1_SUSPEND:
1121 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1122 break;
1123 case ACLK_USB3OTG0:
1124 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1125 break;
1126 case ACLK_USB3OTG1:
1127 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1128 break;
1129 case ACLK_USB3_RKSOC_AXI_PERF:
1130 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1131 break;
1132 case ACLK_USB3:
1133 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1134 break;
1135 case ACLK_USB3_GRF:
1136 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1137 break;
1138 case HCLK_HOST0:
1139 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1140 break;
1141 case HCLK_HOST0_ARB:
1142 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1143 break;
1144 case HCLK_HOST1:
1145 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1146 break;
1147 case HCLK_HOST1_ARB:
1148 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1149 break;
1150 case SCLK_UPHY0_TCPDPHY_REF:
1151 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1152 break;
1153 case SCLK_UPHY0_TCPDCORE:
1154 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1155 break;
1156 case SCLK_UPHY1_TCPDPHY_REF:
1157 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1158 break;
1159 case SCLK_UPHY1_TCPDCORE:
1160 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1161 break;
1162 case SCLK_PCIEPHY_REF:
1163 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1164 break;
1165 default:
1166 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1167 return -ENOENT;
1168 }
1169
1170 return 0;
1171}
1172
1173static int rk3399_clk_disable(struct clk *clk)
1174{
1175 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1176
1177 switch (clk->id) {
1178 case SCLK_MAC:
1179 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1180 break;
1181 case SCLK_MAC_RX:
1182 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1183 break;
1184 case SCLK_MAC_TX:
1185 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1186 break;
1187 case SCLK_MACREF:
1188 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1189 break;
1190 case SCLK_MACREF_OUT:
1191 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1192 break;
1193 case SCLK_USB2PHY0_REF:
1194 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1195 break;
1196 case SCLK_USB2PHY1_REF:
1197 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1198 break;
1199 case ACLK_GMAC:
1200 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1201 break;
1202 case PCLK_GMAC:
1203 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1204 break;
1205 case SCLK_USB3OTG0_REF:
1206 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1207 break;
1208 case SCLK_USB3OTG1_REF:
1209 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1210 break;
1211 case SCLK_USB3OTG0_SUSPEND:
1212 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1213 break;
1214 case SCLK_USB3OTG1_SUSPEND:
1215 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1216 break;
1217 case ACLK_USB3OTG0:
1218 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1219 break;
1220 case ACLK_USB3OTG1:
1221 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1222 break;
1223 case ACLK_USB3_RKSOC_AXI_PERF:
1224 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1225 break;
1226 case ACLK_USB3:
1227 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1228 break;
1229 case ACLK_USB3_GRF:
1230 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1231 break;
1232 case HCLK_HOST0:
1233 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1234 break;
1235 case HCLK_HOST0_ARB:
1236 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1237 break;
1238 case HCLK_HOST1:
1239 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1240 break;
1241 case HCLK_HOST1_ARB:
1242 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1243 break;
1244 case SCLK_UPHY0_TCPDPHY_REF:
1245 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1246 break;
1247 case SCLK_UPHY0_TCPDCORE:
1248 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1249 break;
1250 case SCLK_UPHY1_TCPDPHY_REF:
1251 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1252 break;
1253 case SCLK_UPHY1_TCPDCORE:
1254 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1255 break;
1256 case SCLK_PCIEPHY_REF:
1257 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1258 break;
1259 default:
1260 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1261 return -ENOENT;
1262 }
1263
1264 return 0;
1265}
1266
1267static struct clk_ops rk3399_clk_ops = {
1268 .get_rate = rk3399_clk_get_rate,
1269 .set_rate = rk3399_clk_set_rate,
1270#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1271 .set_parent = rk3399_clk_set_parent,
1272#endif
1273 .enable = rk3399_clk_enable,
1274 .disable = rk3399_clk_disable,
1275};
1276
1277#ifdef CONFIG_SPL_BUILD
1278static void rkclk_init(struct rockchip_cru *cru)
1279{
1280 u32 aclk_div;
1281 u32 hclk_div;
1282 u32 pclk_div;
1283
1284 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1285 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1286
1287
1288
1289
1290
1291 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1292 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1293 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1294
1295
1296 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1297 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1298
1299
1300 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1301 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1302
1303 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1304 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1305 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1306
1307 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1308 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1309 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1310
1311 rk_clrsetreg(&cru->clksel_con[14],
1312 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1313 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1314 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1315 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1316 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1317 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1318
1319
1320 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1321 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1322
1323 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1324 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1325 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1326
1327 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1328 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1329 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1330
1331 rk_clrsetreg(&cru->clksel_con[23],
1332 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1333 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1334 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1335 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1336 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1337 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1338
1339
1340 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1341 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1342 GPLL_HZ && (hclk_div < 0x1f));
1343
1344 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1345 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1346 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1347
1348 rk_clrsetreg(&cru->clksel_con[25],
1349 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1350 HCLK_PERILP1_PLL_SEL_MASK,
1351 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1352 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1353 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1354}
1355#endif
1356
1357static int rk3399_clk_probe(struct udevice *dev)
1358{
1359#ifdef CONFIG_SPL_BUILD
1360 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1361
1362#if CONFIG_IS_ENABLED(OF_PLATDATA)
1363 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1364
1365 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1366#endif
1367 rkclk_init(priv->cru);
1368#endif
1369 return 0;
1370}
1371
1372static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1373{
1374#if !CONFIG_IS_ENABLED(OF_PLATDATA)
1375 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1376
1377 priv->cru = dev_read_addr_ptr(dev);
1378#endif
1379 return 0;
1380}
1381
1382static int rk3399_clk_bind(struct udevice *dev)
1383{
1384 int ret;
1385 struct udevice *sys_child;
1386 struct sysreset_reg *priv;
1387
1388
1389 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1390 &sys_child);
1391 if (ret) {
1392 debug("Warning: No sysreset driver: ret=%d\n", ret);
1393 } else {
1394 priv = malloc(sizeof(struct sysreset_reg));
1395 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1396 glb_srst_fst_value);
1397 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1398 glb_srst_snd_value);
1399 sys_child->priv = priv;
1400 }
1401
1402#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1403 ret = offsetof(struct rockchip_cru, softrst_con[0]);
1404 ret = rockchip_reset_bind(dev, ret, 21);
1405 if (ret)
1406 debug("Warning: software reset driver bind faile\n");
1407#endif
1408
1409 return 0;
1410}
1411
1412static const struct udevice_id rk3399_clk_ids[] = {
1413 { .compatible = "rockchip,rk3399-cru" },
1414 { }
1415};
1416
1417U_BOOT_DRIVER(clk_rk3399) = {
1418 .name = "rockchip_rk3399_cru",
1419 .id = UCLASS_CLK,
1420 .of_match = rk3399_clk_ids,
1421 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1422 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1423 .ops = &rk3399_clk_ops,
1424 .bind = rk3399_clk_bind,
1425 .probe = rk3399_clk_probe,
1426#if CONFIG_IS_ENABLED(OF_PLATDATA)
1427 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1428#endif
1429};
1430
1431static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1432{
1433 u32 div, con;
1434
1435 switch (clk_id) {
1436 case SCLK_I2C0_PMU:
1437 con = readl(&pmucru->pmucru_clksel[2]);
1438 div = I2C_CLK_DIV_VALUE(con, 0);
1439 break;
1440 case SCLK_I2C4_PMU:
1441 con = readl(&pmucru->pmucru_clksel[3]);
1442 div = I2C_CLK_DIV_VALUE(con, 4);
1443 break;
1444 case SCLK_I2C8_PMU:
1445 con = readl(&pmucru->pmucru_clksel[2]);
1446 div = I2C_CLK_DIV_VALUE(con, 8);
1447 break;
1448 default:
1449 printf("do not support this i2c bus\n");
1450 return -EINVAL;
1451 }
1452
1453 return DIV_TO_RATE(PPLL_HZ, div);
1454}
1455
1456static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1457 uint hz)
1458{
1459 int src_clk_div;
1460
1461 src_clk_div = PPLL_HZ / hz;
1462 assert(src_clk_div - 1 < 127);
1463
1464 switch (clk_id) {
1465 case SCLK_I2C0_PMU:
1466 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1467 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1468 break;
1469 case SCLK_I2C4_PMU:
1470 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1471 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1472 break;
1473 case SCLK_I2C8_PMU:
1474 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1475 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1476 break;
1477 default:
1478 printf("do not support this i2c bus\n");
1479 return -EINVAL;
1480 }
1481
1482 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1483}
1484
1485static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1486{
1487 u32 div, con;
1488
1489
1490 con = readl(&pmucru->pmucru_clksel[0]);
1491 div = con & PMU_PCLK_DIV_CON_MASK;
1492
1493 return DIV_TO_RATE(PPLL_HZ, div);
1494}
1495
1496static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1497{
1498 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1499 ulong rate = 0;
1500
1501 switch (clk->id) {
1502 case PLL_PPLL:
1503 return PPLL_HZ;
1504 case PCLK_RKPWM_PMU:
1505 rate = rk3399_pwm_get_clk(priv->pmucru);
1506 break;
1507 case SCLK_I2C0_PMU:
1508 case SCLK_I2C4_PMU:
1509 case SCLK_I2C8_PMU:
1510 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1511 break;
1512 default:
1513 return -ENOENT;
1514 }
1515
1516 return rate;
1517}
1518
1519static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1520{
1521 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1522 ulong ret = 0;
1523
1524 switch (clk->id) {
1525 case PLL_PPLL:
1526
1527
1528
1529
1530
1531 return PPLL_HZ;
1532 case SCLK_I2C0_PMU:
1533 case SCLK_I2C4_PMU:
1534 case SCLK_I2C8_PMU:
1535 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1536 break;
1537 default:
1538 return -ENOENT;
1539 }
1540
1541 return ret;
1542}
1543
1544static struct clk_ops rk3399_pmuclk_ops = {
1545 .get_rate = rk3399_pmuclk_get_rate,
1546 .set_rate = rk3399_pmuclk_set_rate,
1547};
1548
1549#ifndef CONFIG_SPL_BUILD
1550static void pmuclk_init(struct rk3399_pmucru *pmucru)
1551{
1552 u32 pclk_div;
1553
1554
1555 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1556
1557
1558 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1559 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1560 PMU_PCLK_DIV_CON_MASK,
1561 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1562}
1563#endif
1564
1565static int rk3399_pmuclk_probe(struct udevice *dev)
1566{
1567#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1568 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1569#endif
1570
1571#if CONFIG_IS_ENABLED(OF_PLATDATA)
1572 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1573
1574 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1575#endif
1576
1577#ifndef CONFIG_SPL_BUILD
1578 pmuclk_init(priv->pmucru);
1579#endif
1580 return 0;
1581}
1582
1583static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1584{
1585#if !CONFIG_IS_ENABLED(OF_PLATDATA)
1586 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1587
1588 priv->pmucru = dev_read_addr_ptr(dev);
1589#endif
1590 return 0;
1591}
1592
1593static int rk3399_pmuclk_bind(struct udevice *dev)
1594{
1595#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1596 int ret;
1597
1598 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1599 ret = rockchip_reset_bind(dev, ret, 2);
1600 if (ret)
1601 debug("Warning: software reset driver bind faile\n");
1602#endif
1603 return 0;
1604}
1605
1606static const struct udevice_id rk3399_pmuclk_ids[] = {
1607 { .compatible = "rockchip,rk3399-pmucru" },
1608 { }
1609};
1610
1611U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1612 .name = "rockchip_rk3399_pmucru",
1613 .id = UCLASS_CLK,
1614 .of_match = rk3399_pmuclk_ids,
1615 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1616 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1617 .ops = &rk3399_pmuclk_ops,
1618 .probe = rk3399_pmuclk_probe,
1619 .bind = rk3399_pmuclk_bind,
1620#if CONFIG_IS_ENABLED(OF_PLATDATA)
1621 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1622#endif
1623};
1624
