LXR uboot/drivers/i2c/mxc

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * i2c driver for Freescale i.MX series
   4 *
   5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
   7 * Copyright 2020 NXP
   8 *
   9 * Based on i2c-imx.c from linux kernel:
  10 *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  11 *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  12 *  Copyright (C) 2007 RightHand Technologies, Inc.
  13 *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  14 *
  15 */
  16
  17#include <common.h>
  18#include <log.h>
  19#include <asm/arch/clock.h>
  20#include <asm/arch/imx-regs.h>
  21#include <dm/device_compat.h>
  22#include <linux/delay.h>
  23#include <linux/errno.h>
  24#include <asm/mach-imx/mxc_i2c.h>
  25#include <asm/mach-imx/sys_proto.h>
  26#include <asm/io.h>
  27#include <i2c.h>
  28#include <watchdog.h>
  29#include <dm.h>
  30#include <dm/pinctrl.h>
  31#include <fdtdec.h>
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35#define I2C_QUIRK_FLAG          (1 << 0)
  36
  37#define IMX_I2C_REGSHIFT        2
  38#define VF610_I2C_REGSHIFT      0
  39
  40#define I2C_EARLY_INIT_INDEX            0
  41#ifdef CONFIG_SYS_I2C_IFDR_DIV
  42#define I2C_IFDR_DIV_CONSERVATIVE       CONFIG_SYS_I2C_IFDR_DIV
  43#else
  44#define I2C_IFDR_DIV_CONSERVATIVE       0x7e
  45#endif
  46
  47/* Register index */
  48#define IADR    0
  49#define IFDR    1
  50#define I2CR    2
  51#define I2SR    3
  52#define I2DR    4
  53
  54#define I2CR_IIEN       (1 << 6)
  55#define I2CR_MSTA       (1 << 5)
  56#define I2CR_MTX        (1 << 4)
  57#define I2CR_TX_NO_AK   (1 << 3)
  58#define I2CR_RSTA       (1 << 2)
  59
  60#define I2SR_ICF        (1 << 7)
  61#define I2SR_IBB        (1 << 5)
  62#define I2SR_IAL        (1 << 4)
  63#define I2SR_IIF        (1 << 1)
  64#define I2SR_RX_NO_AK   (1 << 0)
  65
  66#ifdef I2C_QUIRK_REG
  67#define I2CR_IEN        (0 << 7)
  68#define I2CR_IDIS       (1 << 7)
  69#define I2SR_IIF_CLEAR  (1 << 1)
  70#else
  71#define I2CR_IEN        (1 << 7)
  72#define I2CR_IDIS       (0 << 7)
  73#define I2SR_IIF_CLEAR  (0 << 1)
  74#endif
  75
  76#ifdef I2C_QUIRK_REG
  77static u16 i2c_clk_div[60][2] = {
  78        { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
  79        { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
  80        { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
  81        { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
  82        { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
  83        { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
  84        { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
  85        { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
  86        { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
  87        { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
  88        { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
  89        { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  90        { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  91        { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  92        { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  93};
  94#else
  95static u16 i2c_clk_div[50][2] = {
  96        { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
  97        { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
  98        { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
  99        { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 100        { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 101        { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 102        { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 103        { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 104        { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 105        { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 106        { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 107        { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 108        { 3072, 0x1E }, { 3840, 0x1F }
 109};
 110#endif
 111
 112#ifndef CONFIG_SYS_MXC_I2C1_SPEED
 113#define CONFIG_SYS_MXC_I2C1_SPEED 100000
 114#endif
 115#ifndef CONFIG_SYS_MXC_I2C2_SPEED
 116#define CONFIG_SYS_MXC_I2C2_SPEED 100000
 117#endif
 118#ifndef CONFIG_SYS_MXC_I2C3_SPEED
 119#define CONFIG_SYS_MXC_I2C3_SPEED 100000
 120#endif
 121#ifndef CONFIG_SYS_MXC_I2C4_SPEED
 122#define CONFIG_SYS_MXC_I2C4_SPEED 100000
 123#endif
 124
 125#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 126#define CONFIG_SYS_MXC_I2C1_SLAVE 0
 127#endif
 128#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
 129#define CONFIG_SYS_MXC_I2C2_SLAVE 0
 130#endif
 131#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 132#define CONFIG_SYS_MXC_I2C3_SLAVE 0
 133#endif
 134#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
 135#define CONFIG_SYS_MXC_I2C4_SLAVE 0
 136#endif
 137
 138/*
 139 * Calculate and set proper clock divider
 140 */
 141static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
 142{
 143        unsigned int i2c_clk_rate;
 144        unsigned int div;
 145        u8 clk_div;
 146
 147#if defined(CONFIG_MX31)
 148        struct clock_control_regs *sc_regs =
 149                (struct clock_control_regs *)CCM_BASE;
 150
 151        /* start the required I2C clock */
 152        writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 153                &sc_regs->cgr0);
 154#endif
 155
 156        /* Divider value calculation */
 157#if CONFIG_IS_ENABLED(CLK)
 158        i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
 159#else
 160        i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
 161#endif
 162
 163        div = (i2c_clk_rate + rate - 1) / rate;
 164        if (div < i2c_clk_div[0][0])
 165                clk_div = 0;
 166        else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 167                clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 168        else
 169                for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 170                        ;
 171
 172        /* Store divider value */
 173        return clk_div;
 174}
 175
 176/*
 177 * Set I2C Bus speed
 178 */
 179static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
 180{
 181        ulong base = i2c_bus->base;
 182        bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 183        u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
 184        u8 idx = i2c_clk_div[clk_idx][1];
 185        int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 186
 187        if (!base)
 188                return -EINVAL;
 189
 190        /* Store divider value */
 191        writeb(idx, base + (IFDR << reg_shift));
 192
 193        /* Reset module */
 194        writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 195        writeb(0, base + (I2SR << reg_shift));
 196        return 0;
 197}
 198
 199#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 200#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 201#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
 202
 203static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
 204{
 205        unsigned sr;
 206        ulong elapsed;
 207        bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 208        int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 209        ulong base = i2c_bus->base;
 210        ulong start_time = get_timer(0);
 211        for (;;) {
 212                sr = readb(base + (I2SR << reg_shift));
 213                if (sr & I2SR_IAL) {
 214                        if (quirk)
 215                                writeb(sr | I2SR_IAL, base +
 216                                       (I2SR << reg_shift));
 217                        else
 218                                writeb(sr & ~I2SR_IAL, base +
 219                                       (I2SR << reg_shift));
 220                        printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
 221                                __func__, sr, readb(base + (I2CR << reg_shift)),
 222                                state);
 223                        return -ERESTART;
 224                }
 225                if ((sr & (state >> 8)) == (unsigned char)state)
 226                        return sr;
 227                WATCHDOG_RESET();
 228                elapsed = get_timer(start_time);
 229                if (elapsed > (CONFIG_SYS_HZ / 10))     /* .1 seconds */
 230                        break;
 231        }
 232        printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
 233               sr, readb(base + (I2CR << reg_shift)), state);
 234        return -ETIMEDOUT;
 235}
 236
 237static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
 238{
 239        int ret;
 240        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 241                        VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 242        ulong base = i2c_bus->base;
 243
 244        writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 245        writeb(byte, base + (I2DR << reg_shift));
 246
 247        ret = wait_for_sr_state(i2c_bus, ST_IIF);
 248        if (ret < 0)
 249                return ret;
 250        if (ret & I2SR_RX_NO_AK)
 251                return -EREMOTEIO;
 252        return 0;
 253}
 254
 255/*
 256 * Stub implementations for outer i2c slave operations.
 257 */
 258void __i2c_force_reset_slave(void)
 259{
 260}
 261void i2c_force_reset_slave(void)
 262        __attribute__((weak, alias("__i2c_force_reset_slave")));
 263
 264/*
 265 * Stop I2C transaction
 266 */
 267static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
 268{
 269        int ret;
 270        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 271                        VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 272        ulong base = i2c_bus->base;
 273        unsigned int temp = readb(base + (I2CR << reg_shift));
 274
 275        temp &= ~(I2CR_MSTA | I2CR_MTX);
 276        writeb(temp, base + (I2CR << reg_shift));
 277        ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 278        if (ret < 0)
 279                printf("%s:trigger stop failed\n", __func__);
 280}
 281
 282/*
 283 * Send start signal, chip address and
 284 * write register address
 285 */
 286static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
 287                              u32 addr, int alen)
 288{
 289        unsigned int temp;
 290        int ret;
 291        bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
 292        ulong base = i2c_bus->base;
 293        int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 294
 295        /* Reset i2c slave */
 296        i2c_force_reset_slave();
 297
 298        /* Enable I2C controller */
 299        if (quirk)
 300                ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
 301        else
 302                ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
 303
 304        if (ret) {
 305                writeb(I2CR_IEN, base + (I2CR << reg_shift));
 306                /* Wait for controller to be stable */
 307                udelay(50);
 308        }
 309
 310        if (readb(base + (IADR << reg_shift)) == (chip << 1))
 311                writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
 312        writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 313        ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
 314        if (ret < 0)
 315                return ret;
 316
 317        /* Start I2C transaction */
 318        temp = readb(base + (I2CR << reg_shift));
 319        temp |= I2CR_MSTA;
 320        writeb(temp, base + (I2CR << reg_shift));
 321
 322        ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
 323        if (ret < 0)
 324                return ret;
 325
 326        temp |= I2CR_MTX | I2CR_TX_NO_AK;
 327        writeb(temp, base + (I2CR << reg_shift));
 328
 329        if (alen >= 0)  {
 330                /* write slave address */
 331                ret = tx_byte(i2c_bus, chip << 1);
 332                if (ret < 0)
 333                        return ret;
 334
 335                while (alen--) {
 336                        ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
 337                        if (ret < 0)
 338                                return ret;
 339                }
 340        }
 341
 342        return 0;
 343}
 344
 345#if !defined(I2C2_BASE_ADDR)
 346#define I2C2_BASE_ADDR  0
 347#endif
 348
 349#if !defined(I2C3_BASE_ADDR)
 350#define I2C3_BASE_ADDR  0
 351#endif
 352
 353#if !defined(I2C4_BASE_ADDR)
 354#define I2C4_BASE_ADDR  0
 355#endif
 356
 357#if !defined(I2C5_BASE_ADDR)
 358#define I2C5_BASE_ADDR 0
 359#endif
 360
 361#if !defined(I2C6_BASE_ADDR)
 362#define I2C6_BASE_ADDR 0
 363#endif
 364
 365#if !defined(I2C7_BASE_ADDR)
 366#define I2C7_BASE_ADDR 0
 367#endif
 368
 369#if !defined(I2C8_BASE_ADDR)
 370#define I2C8_BASE_ADDR 0
 371#endif
 372
 373static struct mxc_i2c_bus mxc_i2c_buses[] = {
 374#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
 375        defined(CONFIG_FSL_LAYERSCAPE)
 376        { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
 377        { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
 378        { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
 379        { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
 380        { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
 381        { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
 382        { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
 383        { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
 384#else
 385        { 0, I2C1_BASE_ADDR, 0 },
 386        { 1, I2C2_BASE_ADDR, 0 },
 387        { 2, I2C3_BASE_ADDR, 0 },
 388        { 3, I2C4_BASE_ADDR, 0 },
 389        { 4, I2C5_BASE_ADDR, 0 },
 390        { 5, I2C6_BASE_ADDR, 0 },
 391        { 6, I2C7_BASE_ADDR, 0 },
 392        { 7, I2C8_BASE_ADDR, 0 },
 393#endif
 394};
 395
 396#ifndef CONFIG_DM_I2C
 397int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 398{
 399        if (i2c_bus && i2c_bus->idle_bus_fn)
 400                return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
 401        return 0;
 402}
 403#else
 404/*
 405 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
 406 * "
 407 *  scl-gpios: specify the gpio related to SCL pin
 408 *  sda-gpios: specify the gpio related to SDA pin
 409 *  add pinctrl to configure i2c pins to gpio function for i2c
 410 *  bus recovery, call it "gpio" state
 411 * "
 412 *
 413 * The i2c_idle_bus is an implementation following Linux Kernel.
 414 */
 415int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
 416{
 417        struct udevice *bus = i2c_bus->bus;
 418        struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
 419        struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
 420        struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
 421        int sda, scl, idle_sclks;
 422        int i, ret = 0;
 423        ulong elapsed, start_time;
 424
 425        if (pinctrl_select_state(bus, "gpio")) {
 426                dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
 427                /*
 428                 * GPIO pinctrl for i2c force idle is not a must,
 429                 * but it is strongly recommended to be used.
 430                 * Because it can help you to recover from bad
 431                 * i2c bus state. Do not return failure, because
 432                 * it is not a must.
 433                 */
 434                return 0;
 435        }
 436
 437        dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 438        dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 439        scl = dm_gpio_get_value(scl_gpio);
 440        sda = dm_gpio_get_value(sda_gpio);
 441
 442        if ((sda & scl) == 1)
 443                goto exit;              /* Bus is idle already */
 444
 445        /*
 446         * In most cases it is just enough to generate 8 + 1 SCLK
 447         * clocks to recover I2C slave device from 'stuck' state
 448         * (when for example SW reset was performed, in the middle of
 449         * I2C transmission).
 450         *
 451         * However, there are devices which send data in packets of
 452         * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
 453         * clocks.
 454         */
 455        idle_sclks = 8 + 1;
 456
 457        if (i2c->max_transaction_bytes > 0)
 458                idle_sclks = i2c->max_transaction_bytes * 8 + 1;
 459        /* Send high and low on the SCL line */
 460        for (i = 0; i < idle_sclks; i++) {
 461                dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
 462                dm_gpio_set_value(scl_gpio, 0);
 463                udelay(50);
 464                dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 465                udelay(50);
 466        }
 467        start_time = get_timer(0);
 468        for (;;) {
 469                dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
 470                dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
 471                scl = dm_gpio_get_value(scl_gpio);
 472                sda = dm_gpio_get_value(sda_gpio);
 473                if ((sda & scl) == 1)
 474                        break;
 475                WATCHDOG_RESET();
 476                elapsed = get_timer(start_time);
 477                if (elapsed > (CONFIG_SYS_HZ / 5)) {    /* .2 seconds */
 478                        ret = -EBUSY;
 479                        printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
 480                        break;
 481                }
 482        }
 483
 484exit:
 485        pinctrl_select_state(bus, "default");
 486        return ret;
 487}
 488#endif
 489/*
 490 * Early init I2C for prepare read the clk through I2C.
 491 */
 492void i2c_early_init_f(void)
 493{
 494        ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
 495        bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
 496                                        & I2C_QUIRK_FLAG ? true : false;
 497        int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 498
 499        /* Set I2C divider value */
 500        writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
 501        /* Reset module */
 502        writeb(I2CR_IDIS, base + (I2CR << reg_shift));
 503        writeb(0, base + (I2SR << reg_shift));
 504        /* Enable I2C */
 505        writeb(I2CR_IEN, base + (I2CR << reg_shift));
 506}
 507
 508static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
 509                             u32 addr, int alen)
 510{
 511        int retry;
 512        int ret;
 513        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 514                        VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 515
 516        if (!i2c_bus->base)
 517                return -EINVAL;
 518
 519        for (retry = 0; retry < 3; retry++) {
 520                ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
 521                if (ret >= 0)
 522                        return 0;
 523                i2c_imx_stop(i2c_bus);
 524                if (ret == -EREMOTEIO)
 525                        return ret;
 526
 527                printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
 528                                retry);
 529                if (ret != -ERESTART)
 530                        /* Disable controller */
 531                        writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
 532                udelay(100);
 533                if (i2c_idle_bus(i2c_bus) < 0)
 534                        break;
 535        }
 536        printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
 537        return ret;
 538}
 539
 540
 541static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
 542                          int len)
 543{
 544        int i, ret = 0;
 545
 546        debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
 547        debug("write_data: ");
 548        /* use rc for counter */
 549        for (i = 0; i < len; ++i)
 550                debug(" 0x%02x", buf[i]);
 551        debug("\n");
 552
 553        for (i = 0; i < len; i++) {
 554                ret = tx_byte(i2c_bus, buf[i]);
 555                if (ret < 0) {
 556                        debug("i2c_write_data(): rc=%d\n", ret);
 557                        break;
 558                }
 559        }
 560
 561        return ret;
 562}
 563
 564/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
 565 * final message of a transaction.  If not, it switches the bus back to TX mode
 566 * and does not send a STOP, leaving the bus in a state where a repeated start
 567 * and address can be sent for another message.
 568 */
 569static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
 570                         int len, bool last)
 571{
 572        int ret;
 573        unsigned int temp;
 574        int i;
 575        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 576                        VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 577        ulong base = i2c_bus->base;
 578
 579        debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
 580
 581        /* setup bus to read data */
 582        temp = readb(base + (I2CR << reg_shift));
 583        temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 584        if (len == 1)
 585                temp |= I2CR_TX_NO_AK;
 586        writeb(temp, base + (I2CR << reg_shift));
 587        writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 588        /* dummy read to clear ICF */
 589        readb(base + (I2DR << reg_shift));
 590
 591        /* read data */
 592        for (i = 0; i < len; i++) {
 593                ret = wait_for_sr_state(i2c_bus, ST_IIF);
 594                if (ret < 0) {
 595                        debug("i2c_read_data(): ret=%d\n", ret);
 596                        i2c_imx_stop(i2c_bus);
 597                        return ret;
 598                }
 599
 600                if (i == (len - 1)) {
 601                        /* Final byte has already been received by master!  When
 602                         * we read it from I2DR, the master will start another
 603                         * cycle.  We must program it first to send a STOP or
 604                         * switch to TX to avoid this.
 605                         */
 606                        if (last) {
 607                                i2c_imx_stop(i2c_bus);
 608                        } else {
 609                                /* Final read, no stop, switch back to tx */
 610                                temp = readb(base + (I2CR << reg_shift));
 611                                temp |= I2CR_MTX | I2CR_TX_NO_AK;
 612                                writeb(temp, base + (I2CR << reg_shift));
 613                        }
 614                } else if (i == (len - 2)) {
 615                        /* Master has already recevied penultimate byte.  When
 616                         * we read it from I2DR, master will start RX of final
 617                         * byte.  We must set TX_NO_AK now so it does not ACK
 618                         * that final byte.
 619                         */
 620                        temp = readb(base + (I2CR << reg_shift));
 621                        temp |= I2CR_TX_NO_AK;
 622                        writeb(temp, base + (I2CR << reg_shift));
 623                }
 624
 625                writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
 626                buf[i] = readb(base + (I2DR << reg_shift));
 627        }
 628
 629        /* reuse ret for counter*/
 630        for (ret = 0; ret < len; ++ret)
 631                debug(" 0x%02x", buf[ret]);
 632        debug("\n");
 633
 634        /* It is not clear to me that this is necessary */
 635        if (last)
 636                i2c_imx_stop(i2c_bus);
 637        return 0;
 638}
 639
 640int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 641{
 642        return 1;
 643}
 644
 645int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 646        __attribute__((weak, alias("__enable_i2c_clk")));
 647
 648#ifndef CONFIG_DM_I2C
 649/*
 650 * Read data from I2C device
 651 *
 652 * The transactions use the syntax defined in the Linux kernel I2C docs.
 653 *
 654 * If alen is > 0, then this function will send a transaction of the form:
 655 *     S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
 656 * This is a normal I2C register read: writing the register address, then doing
 657 * a repeated start and reading the data.
 658 *
 659 * If alen == 0, then we get this transaction:
 660 *     S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
 661 * This is somewhat unusual, though valid, transaction.  It addresses the chip
 662 * in write mode, but doesn't actually write any register address or data, then
 663 * does a repeated start and reads data.
 664 *
 665 * If alen < 0, then we get this transaction:
 666 *     S Chip Rd [A] [data] A ... NA P
 667 * The chip is addressed in read mode and then data is read.  No register
 668 * address is written first.  This is perfectly valid on most devices and
 669 * required on some (usually those that don't act like an array of registers).
 670 */
 671static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 672                        int alen, u8 *buf, int len)
 673{
 674        int ret = 0;
 675        u32 temp;
 676        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 677                VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 678        ulong base = i2c_bus->base;
 679
 680        ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 681        if (ret < 0)
 682                return ret;
 683
 684        if (alen >= 0) {
 685                temp = readb(base + (I2CR << reg_shift));
 686                temp |= I2CR_RSTA;
 687                writeb(temp, base + (I2CR << reg_shift));
 688        }
 689
 690        ret = tx_byte(i2c_bus, (chip << 1) | 1);
 691        if (ret < 0) {
 692                i2c_imx_stop(i2c_bus);
 693                return ret;
 694        }
 695
 696        ret = i2c_read_data(i2c_bus, chip, buf, len, true);
 697
 698        i2c_imx_stop(i2c_bus);
 699        return ret;
 700}
 701
 702/*
 703 * Write data to I2C device
 704 *
 705 * If alen > 0, we get this transaction:
 706 *    S Chip Wr [A] addr [A] data [A] ... [A] P
 707 * An ordinary write register command.
 708 *
 709 * If alen == 0, then we get this:
 710 *    S Chip Wr [A] data [A] ... [A] P
 711 * This is a simple I2C write.
 712 *
 713 * If alen < 0, then we get this:
 714 *    S data [A] ... [A] P
 715 * This is most likely NOT something that should be used.  It doesn't send the
 716 * chip address first, so in effect, the first byte of data will be used as the
 717 * address.
 718 */
 719static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
 720                         int alen, const u8 *buf, int len)
 721{
 722        int ret = 0;
 723
 724        ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
 725        if (ret < 0)
 726                return ret;
 727
 728        ret = i2c_write_data(i2c_bus, chip, buf, len);
 729
 730        i2c_imx_stop(i2c_bus);
 731
 732        return ret;
 733}
 734
 735struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
 736{
 737        return &mxc_i2c_buses[adap->hwadapnr];
 738}
 739
 740static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 741                                uint addr, int alen, uint8_t *buffer,
 742                                int len)
 743{
 744        return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 745}
 746
 747static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 748                                uint addr, int alen, uint8_t *buffer,
 749                                int len)
 750{
 751        return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 752}
 753
 754/*
 755 * Test if a chip at a given address responds (probe the chip)
 756 */
 757static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 758{
 759        return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 760}
 761
 762void bus_i2c_init(int index, int speed, int unused,
 763                  int (*idle_bus_fn)(void *p), void *idle_bus_data)
 764{
 765        int ret;
 766
 767        if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
 768                debug("Error i2c index\n");
 769                return;
 770        }
 771
 772        if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
 773                if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
 774                        printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
 775                               (ulong)mxc_i2c_buses[index].base);
 776                        return;
 777                }
 778        }
 779
 780        /*
 781         * Warning: Be careful to allow the assignment to a static
 782         * variable here. This function could be called while U-Boot is
 783         * still running in flash memory. So such assignment is equal
 784         * to write data to flash without erasing.
 785         */
 786        if (idle_bus_fn)
 787                mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
 788        if (idle_bus_data)
 789                mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
 790
 791        ret = enable_i2c_clk(1, index);
 792        if (ret < 0) {
 793                debug("I2C-%d clk fail to enable.\n", index);
 794                return;
 795        }
 796
 797        bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
 798}
 799
 800
 801
 802/*
 803 * Init I2C Bus
 804 */
 805static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 806{
 807        bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
 808}
 809
 810/*
 811 * Set I2C Speed
 812 */
 813static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 814{
 815        return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 816}
 817
 818/*
 819 * Register mxc i2c adapters
 820 */
 821#ifdef CONFIG_SYS_I2C_MXC_I2C1
 822U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
 823                         mxc_i2c_read, mxc_i2c_write,
 824                         mxc_i2c_set_bus_speed,
 825                         CONFIG_SYS_MXC_I2C1_SPEED,
 826                         CONFIG_SYS_MXC_I2C1_SLAVE, 0)
 827#endif
 828
 829#ifdef CONFIG_SYS_I2C_MXC_I2C2
 830U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 831                         mxc_i2c_read, mxc_i2c_write,
 832                         mxc_i2c_set_bus_speed,
 833                         CONFIG_SYS_MXC_I2C2_SPEED,
 834                         CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 835#endif
 836
 837#ifdef CONFIG_SYS_I2C_MXC_I2C3
 838U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 839                         mxc_i2c_read, mxc_i2c_write,
 840                         mxc_i2c_set_bus_speed,
 841                         CONFIG_SYS_MXC_I2C3_SPEED,
 842                         CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 843#endif
 844
 845#ifdef CONFIG_SYS_I2C_MXC_I2C4
 846U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
 847                         mxc_i2c_read, mxc_i2c_write,
 848                         mxc_i2c_set_bus_speed,
 849                         CONFIG_SYS_MXC_I2C4_SPEED,
 850                         CONFIG_SYS_MXC_I2C4_SLAVE, 3)
 851#endif
 852
 853#ifdef CONFIG_SYS_I2C_MXC_I2C5
 854U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
 855                         mxc_i2c_read, mxc_i2c_write,
 856                         mxc_i2c_set_bus_speed,
 857                         CONFIG_SYS_MXC_I2C5_SPEED,
 858                         CONFIG_SYS_MXC_I2C5_SLAVE, 4)
 859#endif
 860
 861#ifdef CONFIG_SYS_I2C_MXC_I2C6
 862U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
 863                         mxc_i2c_read, mxc_i2c_write,
 864                         mxc_i2c_set_bus_speed,
 865                         CONFIG_SYS_MXC_I2C6_SPEED,
 866                         CONFIG_SYS_MXC_I2C6_SLAVE, 5)
 867#endif
 868
 869#ifdef CONFIG_SYS_I2C_MXC_I2C7
 870U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
 871                         mxc_i2c_read, mxc_i2c_write,
 872                         mxc_i2c_set_bus_speed,
 873                         CONFIG_SYS_MXC_I2C7_SPEED,
 874                         CONFIG_SYS_MXC_I2C7_SLAVE, 6)
 875#endif
 876
 877#ifdef CONFIG_SYS_I2C_MXC_I2C8
 878U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
 879                         mxc_i2c_read, mxc_i2c_write,
 880                         mxc_i2c_set_bus_speed,
 881                         CONFIG_SYS_MXC_I2C8_SPEED,
 882                         CONFIG_SYS_MXC_I2C8_SLAVE, 7)
 883#endif
 884
 885#else
 886
 887static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 888{
 889        struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 890
 891        return bus_i2c_set_bus_speed(i2c_bus, speed);
 892}
 893
 894static int mxc_i2c_probe(struct udevice *bus)
 895{
 896        struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 897        const void *fdt = gd->fdt_blob;
 898        int node = dev_of_offset(bus);
 899        fdt_addr_t addr;
 900        int ret, ret2;
 901
 902        i2c_bus->driver_data = dev_get_driver_data(bus);
 903
 904        addr = dev_read_addr(bus);
 905        if (addr == FDT_ADDR_T_NONE)
 906                return -EINVAL;
 907
 908        if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
 909                if (i2c_fused((ulong)addr)) {
 910                        printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
 911                               (ulong)addr);
 912                        return -ENODEV;
 913                }
 914        }
 915
 916        i2c_bus->base = addr;
 917        i2c_bus->index = bus->seq;
 918        i2c_bus->bus = bus;
 919
 920        /* Enable clk */
 921#if CONFIG_IS_ENABLED(CLK)
 922        ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
 923        if (ret) {
 924                printf("Failed to get i2c clk\n");
 925                return ret;
 926        }
 927        ret = clk_enable(&i2c_bus->per_clk);
 928        if (ret) {
 929                printf("Failed to enable i2c clk\n");
 930                return ret;
 931        }
 932#else
 933        ret = enable_i2c_clk(1, bus->seq);
 934        if (ret < 0)
 935                return ret;
 936#endif
 937
 938        /*
 939         * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
 940         * Use gpio to force bus idle when necessary.
 941         */
 942        ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
 943        if (ret < 0) {
 944                debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
 945        } else {
 946                ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
 947                                "scl-gpios", 0, &i2c_bus->scl_gpio,
 948                                GPIOD_IS_OUT);
 949                ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
 950                                "sda-gpios", 0, &i2c_bus->sda_gpio,
 951                                GPIOD_IS_OUT);
 952                if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
 953                    !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
 954                    ret || ret2) {
 955                        dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
 956                        return -EINVAL;
 957                }
 958        }
 959
 960        /*
 961         * Pinmux settings are in board file now, until pinmux is supported,
 962         * we can set pinmux here in probe function.
 963         */
 964
 965        debug("i2c : controller bus %d at %lu , speed %d: ",
 966              bus->seq, i2c_bus->base,
 967              i2c_bus->speed);
 968
 969        return 0;
 970}
 971
 972/* Sends: S Addr Wr [A|NA] P */
 973static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 974                              u32 chip_flags)
 975{
 976        int ret;
 977        struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 978
 979        ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
 980        if (ret < 0) {
 981                debug("%s failed, ret = %d\n", __func__, ret);
 982                return ret;
 983        }
 984
 985        i2c_imx_stop(i2c_bus);
 986
 987        return 0;
 988}
 989
 990static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 991{
 992        struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
 993        int ret = 0;
 994        ulong base = i2c_bus->base;
 995        int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
 996                VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
 997        int read_mode;
 998
 999        /* Here address len is set to -1 to not send any address at first.
1000         * Otherwise i2c_init_transfer will send the chip address with write

1001         * mode set.  This is wrong if the 1st message is read.
1002         */
1003        ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
1004        if (ret < 0) {
1005                debug("i2c_init_transfer error: %d\n", ret);
1006                return ret;
1007        }
1008
1009        read_mode = -1; /* So it's always different on the first message */
1010        for (; nmsgs > 0; nmsgs--, msg++) {
1011                const int msg_is_read = !!(msg->flags & I2C_M_RD);
1012
1013                debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
1014                      msg->len, msg_is_read ? 'R' : 'W');
1015
1016                if (msg_is_read != read_mode) {
1017                        /* Send repeated start if not 1st message */
1018                        if (read_mode != -1) {
1019                                debug("i2c_xfer: [RSTART]\n");
1020                                ret = readb(base + (I2CR << reg_shift));
1021                                ret |= I2CR_RSTA;
1022                                writeb(ret, base + (I2CR << reg_shift));
1023                        }
1024                        debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1025                              msg_is_read ? 'R' : 'W');
1026                        ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1027                        if (ret < 0) {
1028                                debug("i2c_xfer: [STOP]\n");
1029                                i2c_imx_stop(i2c_bus);
1030                                break;
1031                        }
1032                        read_mode = msg_is_read;
1033                }
1034
1035                if (msg->flags & I2C_M_RD)
1036                        ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1037                                            msg->len, nmsgs == 1 ||
1038                                                      (msg->flags & I2C_M_STOP));
1039                else
1040                        ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1041                                             msg->len);
1042
1043                if (ret < 0)
1044                        break;
1045        }
1046
1047        if (ret)
1048                debug("i2c_write: error sending\n");
1049
1050        i2c_imx_stop(i2c_bus);
1051
1052        return ret;
1053}
1054
1055static const struct dm_i2c_ops mxc_i2c_ops = {
1056        .xfer           = mxc_i2c_xfer,
1057        .probe_chip     = mxc_i2c_probe_chip,
1058        .set_bus_speed  = mxc_i2c_set_bus_speed,
1059};
1060
1061static const struct udevice_id mxc_i2c_ids[] = {
1062        { .compatible = "fsl,imx21-i2c", },
1063        { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1064        {}
1065};
1066
1067U_BOOT_DRIVER(i2c_mxc) = {
1068        .name = "i2c_mxc",
1069        .id = UCLASS_I2C,
1070        .of_match = mxc_i2c_ids,
1071        .probe = mxc_i2c_probe,
1072        .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1073        .ops = &mxc_i2c_ops,
1074        .flags = DM_FLAG_PRE_RELOC,
1075};
1076#endif
1077