LXR uboot/drivers/ram/stm32

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5 */
   6
   7#include <common.h>
   8#include <clk.h>
   9#include <dm.h>
  10#include <init.h>
  11#include <log.h>
  12#include <ram.h>
  13#include <asm/io.h>
  14#include <dm/device_compat.h>
  15#include <linux/bitops.h>
  16#include <linux/delay.h>
  17
  18#define MEM_MODE_MASK   GENMASK(2, 0)
  19#define SWP_FMC_OFFSET 10
  20#define SWP_FMC_MASK    GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
  21#define NOT_FOUND       0xff
  22
  23struct stm32_fmc_regs {
  24        /* 0x0 */
  25        u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  26        u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  27        u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  28        u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  29        u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  30        u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  31        u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  32        u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  33        u32 reserved1[24];
  34
  35        /* 0x80 */
  36        u32 pcr;        /* NAND Flash control register */
  37        u32 sr;         /* FIFO status and interrupt register */
  38        u32 pmem;       /* Common memory space timing register */
  39        u32 patt;       /* Attribute memory space timing registers  */
  40        u32 reserved2[1];
  41        u32 eccr;       /* ECC result registers */
  42        u32 reserved3[27];
  43
  44        /* 0x104 */
  45        u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  46        u32 reserved4[1];
  47        u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  48        u32 reserved5[1];
  49        u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  50        u32 reserved6[1];
  51        u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  52        u32 reserved7[8];
  53
  54        /* 0x140 */
  55        u32 sdcr1;      /* SDRAM Control register 1 */
  56        u32 sdcr2;      /* SDRAM Control register 2 */
  57        u32 sdtr1;      /* SDRAM Timing register 1 */
  58        u32 sdtr2;      /* SDRAM Timing register 2 */
  59        u32 sdcmr;      /* SDRAM Mode register */
  60        u32 sdrtr;      /* SDRAM Refresh timing register */
  61        u32 sdsr;       /* SDRAM Status register */
  62};
  63
  64/*
  65 * NOR/PSRAM Control register BCR1
  66 * FMC controller Enable, only availabe for H7
  67 */
  68#define FMC_BCR1_FMCEN          BIT(31)
  69
  70/* Control register SDCR */
  71#define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  72#define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  73#define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  74#define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  75#define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  76#define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  77#define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  78#define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  79#define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  80
  81/* Timings register SDTR */
  82#define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  83#define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  84#define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  85#define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  86#define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  87#define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  88#define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  89
  90#define FMC_SDCMR_NRFS_SHIFT    5
  91
  92#define FMC_SDCMR_MODE_NORMAL           0
  93#define FMC_SDCMR_MODE_START_CLOCK      1
  94#define FMC_SDCMR_MODE_PRECHARGE        2
  95#define FMC_SDCMR_MODE_AUTOREFRESH      3
  96#define FMC_SDCMR_MODE_WRITE_MODE       4
  97#define FMC_SDCMR_MODE_SELFREFRESH      5
  98#define FMC_SDCMR_MODE_POWERDOWN        6
  99
 100#define FMC_SDCMR_BANK_1                BIT(4)
 101#define FMC_SDCMR_BANK_2                BIT(3)
 102
 103#define FMC_SDCMR_MODE_REGISTER_SHIFT   9
 104
 105#define FMC_SDSR_BUSY                   BIT(5)
 106
 107#define FMC_BUSY_WAIT(regs)     do { \
 108                __asm__ __volatile__ ("dsb" : : : "memory"); \
 109                while (regs->sdsr & FMC_SDSR_BUSY) \
 110                        ; \
 111        } while (0)
 112
 113struct stm32_sdram_control {
 114        u8 no_columns;
 115        u8 no_rows;
 116        u8 memory_width;
 117        u8 no_banks;
 118        u8 cas_latency;
 119        u8 sdclk;
 120        u8 rd_burst;
 121        u8 rd_pipe_delay;
 122};
 123
 124struct stm32_sdram_timing {
 125        u8 tmrd;
 126        u8 txsr;
 127        u8 tras;
 128        u8 trc;
 129        u8 trp;
 130        u8 twr;
 131        u8 trcd;
 132};
 133enum stm32_fmc_bank {
 134        SDRAM_BANK1,
 135        SDRAM_BANK2,
 136        MAX_SDRAM_BANK,
 137};
 138
 139enum stm32_fmc_family {
 140        STM32F7_FMC,
 141        STM32H7_FMC,
 142};
 143
 144struct bank_params {
 145        struct stm32_sdram_control *sdram_control;
 146        struct stm32_sdram_timing *sdram_timing;
 147        u32 sdram_ref_count;
 148        enum stm32_fmc_bank target_bank;
 149};
 150
 151struct stm32_sdram_params {
 152        struct stm32_fmc_regs *base;
 153        u8 no_sdram_banks;
 154        struct bank_params bank_params[MAX_SDRAM_BANK];
 155        enum stm32_fmc_family family;
 156};
 157
 158#define SDRAM_MODE_BL_SHIFT     0
 159#define SDRAM_MODE_CAS_SHIFT    4
 160#define SDRAM_MODE_BL           0
 161
 162int stm32_sdram_init(struct udevice *dev)
 163{
 164        struct stm32_sdram_params *params = dev_get_platdata(dev);
 165        struct stm32_sdram_control *control;
 166        struct stm32_sdram_timing *timing;
 167        struct stm32_fmc_regs *regs = params->base;
 168        enum stm32_fmc_bank target_bank;
 169        u32 ctb; /* SDCMR register: Command Target Bank */
 170        u32 ref_count;
 171        u8 i;
 172
 173        /* disable the FMC controller */
 174        if (params->family == STM32H7_FMC)
 175                clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 176
 177        for (i = 0; i < params->no_sdram_banks; i++) {
 178                control = params->bank_params[i].sdram_control;
 179                timing = params->bank_params[i].sdram_timing;
 180                target_bank = params->bank_params[i].target_bank;
 181                ref_count = params->bank_params[i].sdram_ref_count;
 182
 183                writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 184                        | control->cas_latency << FMC_SDCR_CAS_SHIFT
 185                        | control->no_banks << FMC_SDCR_NB_SHIFT
 186                        | control->memory_width << FMC_SDCR_MWID_SHIFT
 187                        | control->no_rows << FMC_SDCR_NR_SHIFT
 188                        | control->no_columns << FMC_SDCR_NC_SHIFT
 189                        | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 190                        | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 191                        &regs->sdcr1);
 192
 193                if (target_bank == SDRAM_BANK2)
 194                        writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
 195                                | control->no_banks << FMC_SDCR_NB_SHIFT
 196                                | control->memory_width << FMC_SDCR_MWID_SHIFT
 197                                | control->no_rows << FMC_SDCR_NR_SHIFT
 198                                | control->no_columns << FMC_SDCR_NC_SHIFT,
 199                                &regs->sdcr2);
 200
 201                writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 202                        | timing->trp << FMC_SDTR_TRP_SHIFT
 203                        | timing->twr << FMC_SDTR_TWR_SHIFT
 204                        | timing->trc << FMC_SDTR_TRC_SHIFT
 205                        | timing->tras << FMC_SDTR_TRAS_SHIFT
 206                        | timing->txsr << FMC_SDTR_TXSR_SHIFT
 207                        | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 208                        &regs->sdtr1);
 209
 210                if (target_bank == SDRAM_BANK2)
 211                        writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 212                                | timing->trp << FMC_SDTR_TRP_SHIFT
 213                                | timing->twr << FMC_SDTR_TWR_SHIFT
 214                                | timing->trc << FMC_SDTR_TRC_SHIFT
 215                                | timing->tras << FMC_SDTR_TRAS_SHIFT
 216                                | timing->txsr << FMC_SDTR_TXSR_SHIFT
 217                                | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 218                                &regs->sdtr2);
 219
 220                if (target_bank == SDRAM_BANK1)
 221                        ctb = FMC_SDCMR_BANK_1;
 222                else
 223                        ctb = FMC_SDCMR_BANK_2;
 224
 225                writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
 226                udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 227                FMC_BUSY_WAIT(regs);
 228
 229                writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
 230                udelay(100);
 231                FMC_BUSY_WAIT(regs);
 232
 233                writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
 234                       &regs->sdcmr);
 235                udelay(100);
 236                FMC_BUSY_WAIT(regs);
 237
 238                writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 239                       | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 240                       << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 241                       &regs->sdcmr);
 242                udelay(100);
 243                FMC_BUSY_WAIT(regs);
 244
 245                writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
 246                FMC_BUSY_WAIT(regs);
 247
 248                /* Refresh timer */
 249                writel(ref_count << 1, &regs->sdrtr);
 250        }
 251
 252        /* enable the FMC controller */
 253        if (params->family == STM32H7_FMC)
 254                setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 255
 256        return 0;
 257}
 258
 259static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 260{
 261        struct stm32_sdram_params *params = dev_get_platdata(dev);
 262        struct bank_params *bank_params;
 263        struct ofnode_phandle_args args;
 264        u32 *syscfg_base;
 265        u32 mem_remap;
 266        u32 swp_fmc;
 267        ofnode bank_node;
 268        char *bank_name;
 269        u8 bank = 0;
 270        int ret;
 271
 272        ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 273                                                 &args);
 274        if (ret) {
 275                dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
 276        } else {
 277                syscfg_base = (u32 *)ofnode_get_addr(args.node);
 278
 279                mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
 280                if (mem_remap != NOT_FOUND) {
 281                        /* set memory mapping selection */
 282                        clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
 283                } else {
 284                        dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
 285                }
 286                
 287                swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
 288                if (swp_fmc != NOT_FOUND) {
 289                        /* set fmc swapping selection */
 290                        clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
 291                } else {
 292                        dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
 293                }
 294
 295                dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
 296        }
 297
 298        dev_for_each_subnode(bank_node, dev) {
 299                /* extract the bank index from DT */
 300                bank_name = (char *)ofnode_get_name(bank_node);
 301                strsep(&bank_name, "@");
 302                if (!bank_name) {
 303                        pr_err("missing sdram bank index");
 304                        return -EINVAL;
 305                }
 306
 307                bank_params = &params->bank_params[bank];
 308                strict_strtoul(bank_name, 10,
 309                               (long unsigned int *)&bank_params->target_bank);
 310
 311                if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 312                        pr_err("Found bank %d , but only bank 0 and 1 are supported",
 313                              bank_params->target_bank);
 314                        return -EINVAL;
 315                }
 316
 317                debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
 318
 319                params->bank_params[bank].sdram_control =
 320                        (struct stm32_sdram_control *)
 321                         ofnode_read_u8_array_ptr(bank_node,
 322                                                  "st,sdram-control",
 323                                                  sizeof(struct stm32_sdram_control));
 324
 325                if (!params->bank_params[bank].sdram_control) {
 326                        pr_err("st,sdram-control not found for %s",
 327                              ofnode_get_name(bank_node));
 328                        return -EINVAL;
 329                }
 330
 331
 332                params->bank_params[bank].sdram_timing =
 333                        (struct stm32_sdram_timing *)
 334                         ofnode_read_u8_array_ptr(bank_node,
 335                                                  "st,sdram-timing",
 336                                                  sizeof(struct stm32_sdram_timing));
 337
 338                if (!params->bank_params[bank].sdram_timing) {
 339                        pr_err("st,sdram-timing not found for %s",
 340                              ofnode_get_name(bank_node));
 341                        return -EINVAL;
 342                }
 343
 344
 345                bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 346                                                "st,sdram-refcount", 8196);
 347                bank++;
 348        }
 349
 350        params->no_sdram_banks = bank;
 351        debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 352
 353        return 0;
 354}
 355
 356static int stm32_fmc_probe(struct udevice *dev)
 357{
 358        struct stm32_sdram_params *params = dev_get_platdata(dev);
 359        int ret;
 360        fdt_addr_t addr;
 361
 362        addr = dev_read_addr(dev);
 363        if (addr == FDT_ADDR_T_NONE)
 364                return -EINVAL;
 365
 366        params->base = (struct stm32_fmc_regs *)addr;
 367        params->family = dev_get_driver_data(dev);
 368
 369#ifdef CONFIG_CLK
 370        struct clk clk;
 371
 372        ret = clk_get_by_index(dev, 0, &clk);
 373        if (ret < 0)
 374                return ret;
 375
 376        ret = clk_enable(&clk);
 377
 378        if (ret) {
 379                dev_err(dev, "failed to enable clock\n");
 380                return ret;
 381        }
 382#endif
 383        ret = stm32_sdram_init(dev);
 384        if (ret)
 385                return ret;
 386
 387        return 0;
 388}
 389
 390static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 391{
 392        return 0;
 393}
 394
 395static struct ram_ops stm32_fmc_ops = {
 396        .get_info = stm32_fmc_get_info,
 397};
 398
 399static const struct udevice_id stm32_fmc_ids[] = {
 400        { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
 401        { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
 402        { }
 403};
 404
 405U_BOOT_DRIVER(stm32_fmc) = {
 406        .name = "stm32_fmc",
 407        .id = UCLASS_RAM,
 408        .of_match = stm32_fmc_ids,
 409        .ops = &stm32_fmc_ops,
 410        .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
 411        .probe = stm32_fmc_probe,
 412        .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
 413};
 414