LXR uboot/drivers/ram/stm32mp1/stm32mp1

   1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4 */
   5
   6#include <common.h>
   7#include <clk.h>
   8#include <log.h>
   9#include <ram.h>
  10#include <reset.h>
  11#include <timer.h>
  12#include <asm/io.h>
  13#include <asm/arch/ddr.h>
  14#include <linux/bitops.h>
  15#include <linux/delay.h>
  16#include <linux/iopoll.h>
  17#include "stm32mp1_ddr.h"
  18#include "stm32mp1_ddr_regs.h"
  19
  20#define RCC_DDRITFCR            0xD8
  21
  22#define RCC_DDRITFCR_DDRCAPBRST         (BIT(14))
  23#define RCC_DDRITFCR_DDRCAXIRST         (BIT(15))
  24#define RCC_DDRITFCR_DDRCORERST         (BIT(16))
  25#define RCC_DDRITFCR_DPHYAPBRST         (BIT(17))
  26#define RCC_DDRITFCR_DPHYRST            (BIT(18))
  27#define RCC_DDRITFCR_DPHYCTLRST         (BIT(19))
  28
  29struct reg_desc {
  30        const char *name;
  31        u16 offset;     /* offset for base address */
  32        u8 par_offset;  /* offset for parameter array */
  33};
  34
  35#define INVALID_OFFSET  0xFF
  36
  37#define DDRCTL_REG(x, y) \
  38        {#x,\
  39         offsetof(struct stm32mp1_ddrctl, x),\
  40         offsetof(struct y, x)}
  41
  42#define DDRPHY_REG(x, y) \
  43        {#x,\
  44         offsetof(struct stm32mp1_ddrphy, x),\
  45         offsetof(struct y, x)}
  46
  47#define DDR_REG_DYN(x) \
  48        {#x,\
  49         offsetof(struct stm32mp1_ddrctl, x),\
  50         INVALID_OFFSET}
  51
  52#define DDRPHY_REG_DYN(x) \
  53        {#x,\
  54         offsetof(struct stm32mp1_ddrphy, x),\
  55         INVALID_OFFSET}
  56
  57/***********************************************************
  58 * PARAMETERS: value get from device tree :
  59 *             size / order need to be aligned with binding
  60 *             modification NOT ALLOWED !!!
  61 ***********************************************************/
  62#define DDRCTL_REG_REG_SIZE     25      /* st,ctl-reg */
  63#define DDRCTL_REG_TIMING_SIZE  12      /* st,ctl-timing */
  64#define DDRCTL_REG_MAP_SIZE     9       /* st,ctl-map */
  65#define DDRCTL_REG_PERF_SIZE    17      /* st,ctl-perf */
  66
  67#define DDRPHY_REG_REG_SIZE     11      /* st,phy-reg */
  68#define DDRPHY_REG_TIMING_SIZE  10      /* st,phy-timing */
  69#define DDRPHY_REG_CAL_SIZE     12      /* st,phy-cal */
  70
  71#define DDRCTL_REG_REG(x)       DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
  72static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
  73        DDRCTL_REG_REG(mstr),
  74        DDRCTL_REG_REG(mrctrl0),
  75        DDRCTL_REG_REG(mrctrl1),
  76        DDRCTL_REG_REG(derateen),
  77        DDRCTL_REG_REG(derateint),
  78        DDRCTL_REG_REG(pwrctl),
  79        DDRCTL_REG_REG(pwrtmg),
  80        DDRCTL_REG_REG(hwlpctl),
  81        DDRCTL_REG_REG(rfshctl0),
  82        DDRCTL_REG_REG(rfshctl3),
  83        DDRCTL_REG_REG(crcparctl0),
  84        DDRCTL_REG_REG(zqctl0),
  85        DDRCTL_REG_REG(dfitmg0),
  86        DDRCTL_REG_REG(dfitmg1),
  87        DDRCTL_REG_REG(dfilpcfg0),
  88        DDRCTL_REG_REG(dfiupd0),
  89        DDRCTL_REG_REG(dfiupd1),
  90        DDRCTL_REG_REG(dfiupd2),
  91        DDRCTL_REG_REG(dfiphymstr),
  92        DDRCTL_REG_REG(odtmap),
  93        DDRCTL_REG_REG(dbg0),
  94        DDRCTL_REG_REG(dbg1),
  95        DDRCTL_REG_REG(dbgcmd),
  96        DDRCTL_REG_REG(poisoncfg),
  97        DDRCTL_REG_REG(pccfg),
  98};
  99
 100#define DDRCTL_REG_TIMING(x)    DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
 101static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
 102        DDRCTL_REG_TIMING(rfshtmg),
 103        DDRCTL_REG_TIMING(dramtmg0),
 104        DDRCTL_REG_TIMING(dramtmg1),
 105        DDRCTL_REG_TIMING(dramtmg2),
 106        DDRCTL_REG_TIMING(dramtmg3),
 107        DDRCTL_REG_TIMING(dramtmg4),
 108        DDRCTL_REG_TIMING(dramtmg5),
 109        DDRCTL_REG_TIMING(dramtmg6),
 110        DDRCTL_REG_TIMING(dramtmg7),
 111        DDRCTL_REG_TIMING(dramtmg8),
 112        DDRCTL_REG_TIMING(dramtmg14),
 113        DDRCTL_REG_TIMING(odtcfg),
 114};
 115
 116#define DDRCTL_REG_MAP(x)       DDRCTL_REG(x, stm32mp1_ddrctrl_map)
 117static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
 118        DDRCTL_REG_MAP(addrmap1),
 119        DDRCTL_REG_MAP(addrmap2),
 120        DDRCTL_REG_MAP(addrmap3),
 121        DDRCTL_REG_MAP(addrmap4),
 122        DDRCTL_REG_MAP(addrmap5),
 123        DDRCTL_REG_MAP(addrmap6),
 124        DDRCTL_REG_MAP(addrmap9),
 125        DDRCTL_REG_MAP(addrmap10),
 126        DDRCTL_REG_MAP(addrmap11),
 127};
 128
 129#define DDRCTL_REG_PERF(x)      DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
 130static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
 131        DDRCTL_REG_PERF(sched),
 132        DDRCTL_REG_PERF(sched1),
 133        DDRCTL_REG_PERF(perfhpr1),
 134        DDRCTL_REG_PERF(perflpr1),
 135        DDRCTL_REG_PERF(perfwr1),
 136        DDRCTL_REG_PERF(pcfgr_0),
 137        DDRCTL_REG_PERF(pcfgw_0),
 138        DDRCTL_REG_PERF(pcfgqos0_0),
 139        DDRCTL_REG_PERF(pcfgqos1_0),
 140        DDRCTL_REG_PERF(pcfgwqos0_0),
 141        DDRCTL_REG_PERF(pcfgwqos1_0),
 142        DDRCTL_REG_PERF(pcfgr_1),
 143        DDRCTL_REG_PERF(pcfgw_1),
 144        DDRCTL_REG_PERF(pcfgqos0_1),
 145        DDRCTL_REG_PERF(pcfgqos1_1),
 146        DDRCTL_REG_PERF(pcfgwqos0_1),
 147        DDRCTL_REG_PERF(pcfgwqos1_1),
 148};
 149
 150#define DDRPHY_REG_REG(x)       DDRPHY_REG(x, stm32mp1_ddrphy_reg)
 151static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
 152        DDRPHY_REG_REG(pgcr),
 153        DDRPHY_REG_REG(aciocr),
 154        DDRPHY_REG_REG(dxccr),
 155        DDRPHY_REG_REG(dsgcr),
 156        DDRPHY_REG_REG(dcr),
 157        DDRPHY_REG_REG(odtcr),
 158        DDRPHY_REG_REG(zq0cr1),
 159        DDRPHY_REG_REG(dx0gcr),
 160        DDRPHY_REG_REG(dx1gcr),
 161        DDRPHY_REG_REG(dx2gcr),
 162        DDRPHY_REG_REG(dx3gcr),
 163};
 164
 165#define DDRPHY_REG_TIMING(x)    DDRPHY_REG(x, stm32mp1_ddrphy_timing)
 166static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
 167        DDRPHY_REG_TIMING(ptr0),
 168        DDRPHY_REG_TIMING(ptr1),
 169        DDRPHY_REG_TIMING(ptr2),
 170        DDRPHY_REG_TIMING(dtpr0),
 171        DDRPHY_REG_TIMING(dtpr1),
 172        DDRPHY_REG_TIMING(dtpr2),
 173        DDRPHY_REG_TIMING(mr0),
 174        DDRPHY_REG_TIMING(mr1),
 175        DDRPHY_REG_TIMING(mr2),
 176        DDRPHY_REG_TIMING(mr3),
 177};
 178
 179#define DDRPHY_REG_CAL(x)       DDRPHY_REG(x, stm32mp1_ddrphy_cal)
 180static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
 181        DDRPHY_REG_CAL(dx0dllcr),
 182        DDRPHY_REG_CAL(dx0dqtr),
 183        DDRPHY_REG_CAL(dx0dqstr),
 184        DDRPHY_REG_CAL(dx1dllcr),
 185        DDRPHY_REG_CAL(dx1dqtr),
 186        DDRPHY_REG_CAL(dx1dqstr),
 187        DDRPHY_REG_CAL(dx2dllcr),
 188        DDRPHY_REG_CAL(dx2dqtr),
 189        DDRPHY_REG_CAL(dx2dqstr),
 190        DDRPHY_REG_CAL(dx3dllcr),
 191        DDRPHY_REG_CAL(dx3dqtr),
 192        DDRPHY_REG_CAL(dx3dqstr),
 193};
 194
 195/**************************************************************
 196 * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
 197 **************************************************************/
 198#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 199static const struct reg_desc ddr_dyn[] = {
 200        DDR_REG_DYN(stat),
 201        DDR_REG_DYN(init0),
 202        DDR_REG_DYN(dfimisc),
 203        DDR_REG_DYN(dfistat),
 204        DDR_REG_DYN(swctl),
 205        DDR_REG_DYN(swstat),
 206        DDR_REG_DYN(pctrl_0),
 207        DDR_REG_DYN(pctrl_1),
 208};
 209
 210#define DDR_REG_DYN_SIZE        ARRAY_SIZE(ddr_dyn)
 211
 212static const struct reg_desc ddrphy_dyn[] = {
 213        DDRPHY_REG_DYN(pir),
 214        DDRPHY_REG_DYN(pgsr),
 215        DDRPHY_REG_DYN(zq0sr0),
 216        DDRPHY_REG_DYN(zq0sr1),
 217        DDRPHY_REG_DYN(dx0gsr0),
 218        DDRPHY_REG_DYN(dx0gsr1),
 219        DDRPHY_REG_DYN(dx1gsr0),
 220        DDRPHY_REG_DYN(dx1gsr1),
 221        DDRPHY_REG_DYN(dx2gsr0),
 222        DDRPHY_REG_DYN(dx2gsr1),
 223        DDRPHY_REG_DYN(dx3gsr0),
 224        DDRPHY_REG_DYN(dx3gsr1),
 225};
 226
 227#define DDRPHY_REG_DYN_SIZE     ARRAY_SIZE(ddrphy_dyn)
 228
 229#endif
 230
 231/*****************************************************************
 232 * REGISTERS ARRAY: used to parse device tree and interactive mode
 233 *****************************************************************/
 234enum reg_type {
 235        REG_REG,
 236        REG_TIMING,
 237        REG_PERF,
 238        REG_MAP,
 239        REGPHY_REG,
 240        REGPHY_TIMING,
 241        REGPHY_CAL,
 242#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 243/* dynamic registers => managed in driver or not changed,
 244 * can be dumped in interactive mode
 245 */
 246        REG_DYN,
 247        REGPHY_DYN,
 248#endif
 249        REG_TYPE_NB
 250};
 251
 252enum base_type {
 253        DDR_BASE,
 254        DDRPHY_BASE,
 255        NONE_BASE
 256};
 257
 258struct ddr_reg_info {
 259        const char *name;
 260        const struct reg_desc *desc;
 261        u8 size;
 262        enum base_type base;
 263};
 264
 265#define DDRPHY_REG_CAL(x)       DDRPHY_REG(x, stm32mp1_ddrphy_cal)
 266
 267const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
 268[REG_REG] = {
 269        "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
 270[REG_TIMING] = {
 271        "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
 272[REG_PERF] = {
 273        "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
 274[REG_MAP] = {
 275        "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
 276[REGPHY_REG] = {
 277        "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
 278[REGPHY_TIMING] = {
 279        "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
 280[REGPHY_CAL] = {
 281        "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
 282#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 283[REG_DYN] = {
 284        "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
 285[REGPHY_DYN] = {
 286        "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
 287#endif
 288
 289};
 290
 291const char *base_name[] = {
 292        [DDR_BASE] = "ctl",
 293        [DDRPHY_BASE] = "phy",
 294};
 295
 296static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
 297{
 298        if (base == DDRPHY_BASE)
 299                return (u32)priv->phy;
 300        else
 301                return (u32)priv->ctl;
 302}
 303
 304static void set_reg(const struct ddr_info *priv,
 305                    enum reg_type type,
 306                    const void *param)
 307{
 308        unsigned int i;
 309        unsigned int *ptr, value;
 310        enum base_type base = ddr_registers[type].base;
 311        u32 base_addr = get_base_addr(priv, base);
 312        const struct reg_desc *desc = ddr_registers[type].desc;
 313
 314        debug("init %s\n", ddr_registers[type].name);
 315        for (i = 0; i < ddr_registers[type].size; i++) {
 316                ptr = (unsigned int *)(base_addr + desc[i].offset);
 317                if (desc[i].par_offset == INVALID_OFFSET) {
 318                        pr_err("invalid parameter offset for %s", desc[i].name);
 319                } else {
 320                        value = *((u32 *)((u32)param +
 321                                               desc[i].par_offset));
 322                        writel(value, ptr);
 323                        debug("[0x%x] %s= 0x%08x\n",
 324                              (u32)ptr, desc[i].name, value);
 325                }
 326        }
 327}
 328
 329#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 330static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
 331{
 332        unsigned int *ptr;
 333
 334        ptr = (unsigned int *)(base_addr + desc->offset);
 335        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 336}
 337
 338static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
 339{
 340        unsigned int *ptr;
 341
 342        ptr = (unsigned int *)(par_addr + desc->par_offset);
 343        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 344}
 345
 346static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
 347{
 348        unsigned int i, j;
 349        const struct reg_desc *desc;
 350
 351        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 352                desc = ddr_registers[i].desc;
 353                for (j = 0; j < ddr_registers[i].size; j++) {
 354                        if (strcmp(name, desc[j].name) == 0) {
 355                                *type = i;
 356                                return &desc[j];
 357                        }
 358                }
 359        }
 360        *type = REG_TYPE_NB;
 361        return NULL;
 362}
 363
 364int stm32mp1_dump_reg(const struct ddr_info *priv,
 365                      const char *name)
 366{
 367        unsigned int i, j;
 368        const struct reg_desc *desc;
 369        u32 base_addr;
 370        enum base_type p_base;
 371        enum reg_type type;
 372        const char *p_name;
 373        enum base_type filter = NONE_BASE;
 374        int result = -1;
 375
 376        if (name) {
 377                if (strcmp(name, base_name[DDR_BASE]) == 0)
 378                        filter = DDR_BASE;
 379                else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
 380                        filter = DDRPHY_BASE;
 381        }
 382
 383        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 384                p_base = ddr_registers[i].base;
 385                p_name = ddr_registers[i].name;
 386                if (!name || (filter == p_base || !strcmp(name, p_name))) {
 387                        result = 0;
 388                        desc = ddr_registers[i].desc;
 389                        base_addr = get_base_addr(priv, p_base);
 390                        printf("==%s.%s==\n", base_name[p_base], p_name);
 391                        for (j = 0; j < ddr_registers[i].size; j++)
 392                                stm32mp1_dump_reg_desc(base_addr, &desc[j]);
 393                }
 394        }
 395        if (result) {
 396                desc = found_reg(name, &type);
 397                if (desc) {
 398                        p_base = ddr_registers[type].base;
 399                        base_addr = get_base_addr(priv, p_base);
 400                        stm32mp1_dump_reg_desc(base_addr, desc);
 401                        result = 0;
 402                }
 403        }
 404        return result;
 405}
 406
 407void stm32mp1_edit_reg(const struct ddr_info *priv,
 408                       char *name, char *string)
 409{
 410        unsigned long *ptr, value;
 411        enum reg_type type;
 412        enum base_type base;
 413        const struct reg_desc *desc;
 414        u32 base_addr;
 415
 416        desc = found_reg(name, &type);
 417
 418        if (!desc) {
 419                printf("%s not found\n", name);
 420                return;
 421        }
 422        if (strict_strtoul(string, 16, &value) < 0) {
 423                printf("invalid value %s\n", string);
 424                return;
 425        }
 426        base = ddr_registers[type].base;
 427        base_addr = get_base_addr(priv, base);
 428        ptr = (unsigned long *)(base_addr + desc->offset);
 429        writel(value, ptr);
 430        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 431}
 432
 433static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
 434                        enum reg_type type)
 435{
 436        u32 par_addr = 0x0;
 437
 438        switch (type) {
 439        case REG_REG:
 440                par_addr = (u32)&config->c_reg;
 441                break;
 442        case REG_TIMING:
 443                par_addr = (u32)&config->c_timing;
 444                break;
 445        case REG_PERF:
 446                par_addr = (u32)&config->c_perf;
 447                break;
 448        case REG_MAP:
 449                par_addr = (u32)&config->c_map;
 450                break;
 451        case REGPHY_REG:
 452                par_addr = (u32)&config->p_reg;
 453                break;
 454        case REGPHY_TIMING:
 455                par_addr = (u32)&config->p_timing;
 456                break;
 457        case REGPHY_CAL:
 458                par_addr = (u32)&config->p_cal;
 459                break;
 460        case REG_DYN:
 461        case REGPHY_DYN:
 462        case REG_TYPE_NB:
 463                par_addr = (u32)NULL;
 464                break;
 465        }
 466
 467        return par_addr;
 468}
 469
 470int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
 471                        const char *name)
 472{
 473        unsigned int i, j;
 474        const struct reg_desc *desc;
 475        u32 par_addr;
 476        enum base_type p_base;
 477        enum reg_type type;
 478        const char *p_name;
 479        enum base_type filter = NONE_BASE;
 480        int result = -EINVAL;
 481
 482        if (name) {
 483                if (strcmp(name, base_name[DDR_BASE]) == 0)
 484                        filter = DDR_BASE;
 485                else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
 486                        filter = DDRPHY_BASE;
 487        }
 488
 489        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 490                par_addr = get_par_addr(config, i);
 491                if (!par_addr)
 492                        continue;
 493                p_base = ddr_registers[i].base;
 494                p_name = ddr_registers[i].name;
 495                if (!name || (filter == p_base || !strcmp(name, p_name))) {
 496                        result = 0;
 497                        desc = ddr_registers[i].desc;
 498                        printf("==%s.%s==\n", base_name[p_base], p_name);
 499                        for (j = 0; j < ddr_registers[i].size; j++)
 500                                stm32mp1_dump_param_desc(par_addr, &desc[j]);
 501                }
 502        }
 503        if (result) {
 504                desc = found_reg(name, &type);
 505                if (desc) {
 506                        par_addr = get_par_addr(config, type);
 507                        if (par_addr) {
 508                                stm32mp1_dump_param_desc(par_addr, desc);
 509                                result = 0;
 510                        }
 511                }
 512        }
 513        return result;
 514}
 515
 516void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
 517                         char *name, char *string)
 518{
 519        unsigned long *ptr, value;
 520        enum reg_type type;
 521        const struct reg_desc *desc;
 522        u32 par_addr;
 523
 524        desc = found_reg(name, &type);
 525        if (!desc) {
 526                printf("%s not found\n", name);
 527                return;
 528        }
 529        if (strict_strtoul(string, 16, &value) < 0) {
 530                printf("invalid value %s\n", string);
 531                return;
 532        }
 533        par_addr = get_par_addr(config, type);
 534        if (!par_addr) {
 535                printf("no parameter %s\n", name);
 536                return;
 537        }
 538        ptr = (unsigned long *)(par_addr + desc->par_offset);
 539        writel(value, ptr);
 540        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 541}
 542#endif
 543
 544__weak bool stm32mp1_ddr_interactive(void *priv,
 545                                     enum stm32mp1_ddr_interact_step step,
 546                                     const struct stm32mp1_ddr_config *config)
 547{
 548        return false;
 549}
 550
 551#define INTERACTIVE(step)\
 552        stm32mp1_ddr_interactive(priv, step, config)
 553
 554static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
 555{
 556        u32 pgsr;
 557        int ret;
 558
 559        ret = readl_poll_timeout(&phy->pgsr, pgsr,
 560                                 pgsr & (DDRPHYC_PGSR_IDONE |
 561                                         DDRPHYC_PGSR_DTERR |
 562                                         DDRPHYC_PGSR_DTIERR |
 563                                         DDRPHYC_PGSR_DFTERR |
 564                                         DDRPHYC_PGSR_RVERR |
 565                                         DDRPHYC_PGSR_RVEIRR),
 566                                1000000);
 567        debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
 568              (u32)&phy->pgsr, pgsr, ret);
 569}
 570
 571void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
 572{
 573        pir |= DDRPHYC_PIR_INIT;
 574        writel(pir, &phy->pir);
 575        debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
 576              (u32)&phy->pir, pir, readl(&phy->pir));
 577
 578        /* need to wait 10 configuration clock before start polling */
 579        udelay(10);
 580
 581        /* Wait DRAM initialization and Gate Training Evaluation complete */
 582        ddrphy_idone_wait(phy);
 583}
 584
 585/* start quasi dynamic register update */
 586static void start_sw_done(struct stm32mp1_ddrctl *ctl)
 587{
 588        clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
 589}
 590
 591/* wait quasi dynamic register update */
 592static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
 593{
 594        int ret;
 595        u32 swstat;
 596
 597        setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
 598
 599        ret = readl_poll_timeout(&ctl->swstat, swstat,
 600                                 swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
 601                                 1000000);
 602        if (ret)
 603                panic("Timeout initialising DRAM : DDR->swstat = %x\n",
 604                      swstat);
 605
 606        debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
 607}
 608
 609/* wait quasi dynamic register update */
 610static void wait_operating_mode(struct ddr_info *priv, int mode)
 611{
 612        u32 stat, val, mask, val2 = 0, mask2 = 0;
 613        int ret;
 614
 615        mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
 616        val = mode;
 617        /* self-refresh due to software => check also STAT.selfref_type */
 618        if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
 619                mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
 620                val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
 621        } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
 622                /* normal mode: handle also automatic self refresh */
 623                mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
 624                        DDRCTRL_STAT_SELFREF_TYPE_MASK;
 625                val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
 626                       DDRCTRL_STAT_SELFREF_TYPE_ASR;
 627        }
 628
 629        ret = readl_poll_timeout(&priv->ctl->stat, stat,
 630                                 ((stat & mask) == val) ||
 631                                 (mask2 && ((stat & mask2) == val2)),
 632                                 1000000);
 633
 634        if (ret)
 635                panic("Timeout DRAM : DDR->stat = %x\n", stat);
 636
 637        debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
 638}
 639
 640void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
 641{
 642        start_sw_done(ctl);
 643        /* quasi-dynamic register update*/
 644        setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
 645        clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
 646                                   DDRCTRL_PWRCTL_SELFREF_EN);
 647        clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 648        wait_sw_done_ack(ctl);
 649}
 650
 651void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
 652                              u32 rfshctl3, u32 pwrctl)
 653{
 654        start_sw_done(ctl);
 655        if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
 656                clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
 657        if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
 658                setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
 659        if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
 660                setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
 661        setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 662        wait_sw_done_ack(ctl);
 663}
 664
 665/* board-specific DDR power initializations. */
 666__weak int board_ddr_power_init(enum ddr_type ddr_type)
 667{
 668        return 0;
 669}
 670
 671__maybe_unused
 672void stm32mp1_ddr_init(struct ddr_info *priv,
 673                       const struct stm32mp1_ddr_config *config)
 674{
 675        u32 pir;
 676        int ret = -EINVAL;
 677        char bus_width;
 678
 679        switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
 680        case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
 681                bus_width = 8;
 682                break;
 683        case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
 684                bus_width = 16;
 685                break;
 686        default:
 687                bus_width = 32;
 688                break;
 689        }
 690
 691
 692        if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 693                ret = board_ddr_power_init(STM32MP_DDR3);
 694        else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
 695                if (bus_width == 32)
 696                        ret = board_ddr_power_init(STM32MP_LPDDR2_32);
 697                else
 698                        ret = board_ddr_power_init(STM32MP_LPDDR2_16);
 699        } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
 700                if (bus_width == 32)
 701                        ret = board_ddr_power_init(STM32MP_LPDDR3_32);
 702                else
 703                        ret = board_ddr_power_init(STM32MP_LPDDR3_16);
 704        }
 705        if (ret)
 706                panic("ddr power init failed\n");
 707
 708start:
 709        debug("name = %s\n", config->info.name);
 710        debug("speed = %d kHz\n", config->info.speed);
 711        debug("size  = 0x%x\n", config->info.size);
 712/*
 713 * 1. Program the DWC_ddr_umctl2 registers
 714 * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
 715 */
 716        /* Assert All DDR part */
 717        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
 718        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
 719        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
 720        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
 721        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
 722        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
 723
 724/* 1.2. start CLOCK */
 725        if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
 726                panic("invalid DRAM clock : %d kHz\n",
 727                      config->info.speed);
 728
 729/* 1.3. deassert reset */
 730        /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
 731        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
 732        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
 733        /* De-assert presetn once the clocks are active
 734         * and stable via DDRCAPBRST bit
 735         */
 736        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
 737
 738/* 1.4. wait 128 cycles to permit initialization of end logic */
 739        udelay(2);
 740        /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
 741
 742        if (INTERACTIVE(STEP_DDR_RESET))
 743                goto start;
 744
 745/* 1.5. initialize registers ddr_umctl2 */
 746        /* Stop uMCTL2 before PHY is ready */
 747        clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 748        debug("[0x%08x] dfimisc = 0x%08x\n",
 749              (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
 750
 751        set_reg(priv, REG_REG, &config->c_reg);
 752        set_reg(priv, REG_TIMING, &config->c_timing);
 753        set_reg(priv, REG_MAP, &config->c_map);
 754
 755        /* skip CTRL init, SDRAM init is done by PHY PUBL */
 756        clrsetbits_le32(&priv->ctl->init0,
 757                        DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
 758                        DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
 759
 760        set_reg(priv, REG_PERF, &config->c_perf);
 761
 762        if (INTERACTIVE(STEP_CTL_INIT))
 763                goto start;
 764
 765/*  2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
 766        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
 767        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
 768        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
 769
 770/*  3. start PHY init by accessing relevant PUBL registers
 771 *    (DXGCR, DCR, PTR*, MR*, DTPR*)
 772 */
 773        set_reg(priv, REGPHY_REG, &config->p_reg);
 774        set_reg(priv, REGPHY_TIMING, &config->p_timing);
 775        if (config->p_cal_present)
 776                set_reg(priv, REGPHY_CAL, &config->p_cal);
 777
 778        if (INTERACTIVE(STEP_PHY_INIT))
 779                goto start;
 780
 781/*  4. Monitor PHY init status by polling PUBL register PGSR.IDONE
 782 *     Perform DDR PHY DRAM initialization and Gate Training Evaluation
 783 */
 784        ddrphy_idone_wait(priv->phy);
 785
 786/*  5. Indicate to PUBL that controller performs SDRAM initialization
 787 *     by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
 788 *     DRAM init is done by PHY, init0.skip_dram.init = 1
 789 */
 790        pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
 791              DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
 792
 793        if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 794                pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
 795
 796        stm32mp1_ddrphy_init(priv->phy, pir);
 797
 798/*  6. SET DFIMISC.dfi_init_complete_en to 1 */
 799        /* Enable quasi-dynamic register programming*/
 800        start_sw_done(priv->ctl);
 801        setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 802        wait_sw_done_ack(priv->ctl);
 803
 804/*  7. Wait for DWC_ddr_umctl2 to move to normal operation mode
 805 *     by monitoring STAT.operating_mode signal
 806 */
 807        /* wait uMCTL2 ready */
 808
 809        wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
 810
 811        if (config->p_cal_present) {
 812                debug("DDR DQS training skipped.\n");
 813        } else {
 814                debug("DDR DQS training : ");
 815/*  8. Disable Auto refresh and power down by setting
 816 *    - RFSHCTL3.dis_au_refresh = 1
 817 *    - PWRCTL.powerdown_en = 0
 818 *    - DFIMISC.dfiinit_complete_en = 0
 819 */
 820                stm32mp1_refresh_disable(priv->ctl);
 821
 822/*  9. Program PUBL PGCR to enable refresh during training and rank to train
 823 *     not done => keep the programed value in PGCR
 824 */
 825
 826/* 10. configure PUBL PIR register to specify which training step to run */
 827        /* warning : RVTRN  is not supported by this PUBL */
 828                stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
 829
 830/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
 831                ddrphy_idone_wait(priv->phy);
 832
 833/* 12. set back registers in step 8 to the orginal values if desidered */
 834                stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
 835                                         config->c_reg.pwrctl);
 836        } /* if (config->p_cal_present) */
 837
 838        /* enable uMCTL2 AXI port 0 and 1 */
 839        setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
 840        setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
 841
 842        if (INTERACTIVE(STEP_DDR_READY))
 843                goto start;
 844}
 845