uboot/drivers/serial/serial_zynq.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
   5 */
   6
   7#include <clk.h>
   8#include <common.h>
   9#include <debug_uart.h>
  10#include <dm.h>
  11#include <errno.h>
  12#include <fdtdec.h>
  13#include <log.h>
  14#include <watchdog.h>
  15#include <asm/io.h>
  16#include <dm/device_compat.h>
  17#include <linux/bitops.h>
  18#include <linux/compiler.h>
  19#include <serial.h>
  20#include <linux/err.h>
  21
  22#define ZYNQ_UART_SR_TXACTIVE   BIT(11) /* TX active */
  23#define ZYNQ_UART_SR_TXFULL     BIT(4) /* TX FIFO full */
  24#define ZYNQ_UART_SR_RXEMPTY    BIT(1) /* RX FIFO empty */
  25
  26#define ZYNQ_UART_CR_TX_EN      BIT(4) /* TX enabled */
  27#define ZYNQ_UART_CR_RX_EN      BIT(2) /* RX enabled */
  28#define ZYNQ_UART_CR_TXRST      BIT(1) /* TX logic reset */
  29#define ZYNQ_UART_CR_RXRST      BIT(0) /* RX logic reset */
  30
  31#define ZYNQ_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  32
  33struct uart_zynq {
  34        u32 control; /* 0x0 - Control Register [8:0] */
  35        u32 mode; /* 0x4 - Mode Register [10:0] */
  36        u32 reserved1[4];
  37        u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  38        u32 reserved2[4];
  39        u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  40        u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  41        u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  42};
  43
  44struct zynq_uart_platdata {
  45        struct uart_zynq *regs;
  46};
  47
  48/* Set up the baud rate */
  49static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  50                                     unsigned long clock, unsigned long baud)
  51{
  52        /* Calculation results. */
  53        unsigned int calc_bauderror, bdiv, bgen;
  54        unsigned long calc_baud = 0;
  55
  56        /* Covering case where input clock is so slow */
  57        if (clock < 1000000 && baud > 4800)
  58                baud = 4800;
  59
  60        /*                master clock
  61         * Baud rate = ------------------
  62         *              bgen * (bdiv + 1)
  63         *
  64         * Find acceptable values for baud generation.
  65         */
  66        for (bdiv = 4; bdiv < 255; bdiv++) {
  67                bgen = clock / (baud * (bdiv + 1));
  68                if (bgen < 2 || bgen > 65535)
  69                        continue;
  70
  71                calc_baud = clock / (bgen * (bdiv + 1));
  72
  73                /*
  74                 * Use first calculated baudrate with
  75                 * an acceptable (<3%) error
  76                 */
  77                if (baud > calc_baud)
  78                        calc_bauderror = baud - calc_baud;
  79                else
  80                        calc_bauderror = calc_baud - baud;
  81                if (((calc_bauderror * 100) / baud) < 3)
  82                        break;
  83        }
  84
  85        writel(bdiv, &regs->baud_rate_divider);
  86        writel(bgen, &regs->baud_rate_gen);
  87}
  88
  89/* Initialize the UART, with...some settings. */
  90static void _uart_zynq_serial_init(struct uart_zynq *regs)
  91{
  92        /* RX/TX enabled & reset */
  93        writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  94                                        ZYNQ_UART_CR_RXRST, &regs->control);
  95        writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  96}
  97
  98static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
  99{
 100        if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
 101                return -EAGAIN;
 102
 103        writel(c, &regs->tx_rx_fifo);
 104
 105        return 0;
 106}
 107
 108static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 109{
 110        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 111        unsigned long clock;
 112
 113        int ret;
 114        struct clk clk;
 115
 116        ret = clk_get_by_index(dev, 0, &clk);
 117        if (ret < 0) {
 118                dev_err(dev, "failed to get clock\n");
 119                return ret;
 120        }
 121
 122        clock = clk_get_rate(&clk);
 123        if (IS_ERR_VALUE(clock)) {
 124                dev_err(dev, "failed to get rate\n");
 125                return clock;
 126        }
 127        debug("%s: CLK %ld\n", __func__, clock);
 128
 129        ret = clk_enable(&clk);
 130        if (ret && ret != -ENOSYS) {
 131                dev_err(dev, "failed to enable clock\n");
 132                return ret;
 133        }
 134
 135        _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
 136
 137        return 0;
 138}
 139
 140static int zynq_serial_probe(struct udevice *dev)
 141{
 142        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 143        struct uart_zynq *regs = platdata->regs;
 144        u32 val;
 145
 146        /* No need to reinitialize the UART if TX already enabled */
 147        val = readl(&regs->control);
 148        if (val & ZYNQ_UART_CR_TX_EN)
 149                return 0;
 150
 151        _uart_zynq_serial_init(platdata->regs);
 152
 153        return 0;
 154}
 155
 156static int zynq_serial_getc(struct udevice *dev)
 157{
 158        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 159        struct uart_zynq *regs = platdata->regs;
 160
 161        if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
 162                return -EAGAIN;
 163
 164        return readl(&regs->tx_rx_fifo);
 165}
 166
 167static int zynq_serial_putc(struct udevice *dev, const char ch)
 168{
 169        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 170
 171        return _uart_zynq_serial_putc(platdata->regs, ch);
 172}
 173
 174static int zynq_serial_pending(struct udevice *dev, bool input)
 175{
 176        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 177        struct uart_zynq *regs = platdata->regs;
 178
 179        if (input)
 180                return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
 181        else
 182                return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
 183}
 184
 185static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
 186{
 187        struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
 188
 189        platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
 190        if (IS_ERR(platdata->regs))
 191                return PTR_ERR(platdata->regs);
 192
 193        return 0;
 194}
 195
 196static const struct dm_serial_ops zynq_serial_ops = {
 197        .putc = zynq_serial_putc,
 198        .pending = zynq_serial_pending,
 199        .getc = zynq_serial_getc,
 200        .setbrg = zynq_serial_setbrg,
 201};
 202
 203static const struct udevice_id zynq_serial_ids[] = {
 204        { .compatible = "xlnx,xuartps" },
 205        { .compatible = "cdns,uart-r1p8" },
 206        { .compatible = "cdns,uart-r1p12" },
 207        { }
 208};
 209
 210U_BOOT_DRIVER(serial_zynq) = {
 211        .name   = "serial_zynq",
 212        .id     = UCLASS_SERIAL,
 213        .of_match = zynq_serial_ids,
 214        .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
 215        .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
 216        .probe = zynq_serial_probe,
 217        .ops    = &zynq_serial_ops,
 218};
 219
 220#ifdef CONFIG_DEBUG_UART_ZYNQ
 221static inline void _debug_uart_init(void)
 222{
 223        struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 224
 225        _uart_zynq_serial_init(regs);
 226        _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
 227                                 CONFIG_BAUDRATE);
 228}
 229
 230static inline void _debug_uart_putc(int ch)
 231{
 232        struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 233
 234        while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
 235                WATCHDOG_RESET();
 236}
 237
 238DEBUG_UART_FUNCS
 239
 240#endif
 241