1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5485 FireEngine board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5485EVB_H 14#define _M5485EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_HW_WATCHDOG 25#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27#define CONFIG_SLTTMR 28 29#ifdef CONFIG_FSLDMAFEC 30# define CONFIG_MII_INIT 1 31# define CONFIG_HAS_ETH1 32# define CONFIG_SYS_DMA_USE_INTSRAM 1 33# define CONFIG_SYS_DISCOVER_PHY 34# define CONFIG_SYS_RX_ETH_BUFFER 32 35# define CONFIG_SYS_TX_ETH_BUFFER 48 36# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 37/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 38# ifndef CONFIG_SYS_DISCOVER_PHY 39# define FECDUPLEX FULL 40# define FECSPEED _100BASET 41# else 42# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44# endif 45# endif /* CONFIG_SYS_DISCOVER_PHY */ 46 47# define CONFIG_IPADDR 192.162.1.2 48# define CONFIG_NETMASK 255.255.255.0 49# define CONFIG_SERVERIP 192.162.1.1 50# define CONFIG_GATEWAYIP 192.162.1.1 51#endif 52 53#ifdef CONFIG_CMD_USB 54# define CONFIG_USB_OHCI_NEW 55/*# define CONFIG_PCI_OHCI*/ 56# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 57# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 58# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 59# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 60#endif 61 62/* I2C */ 63#define CONFIG_SYS_I2C 64#define CONFIG_SYS_I2C_FSL 65#define CONFIG_SYS_FSL_I2C_SPEED 80000 66#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 67#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 68#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 69 70/* PCI */ 71#ifdef CONFIG_CMD_PCI 72#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 73 74#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 75#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 76#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 77 78#define CONFIG_SYS_PCI_IO_BUS 0x71000000 79#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 80#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 81 82#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 83#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 84#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 85#endif 86 87#define CONFIG_UDP_CHECKSUM 88 89#define CONFIG_HOSTNAME "M548xEVB" 90#define CONFIG_EXTRA_ENV_SETTINGS \ 91 "netdev=eth0\0" \ 92 "loadaddr=10000\0" \ 93 "u-boot=u-boot.bin\0" \ 94 "load=tftp ${loadaddr) ${u-boot}\0" \ 95 "upd=run load; run prog\0" \ 96 "prog=prot off bank 1;" \ 97 "era ff800000 ff83ffff;" \ 98 "cp.b ${loadaddr} ff800000 ${filesize};"\ 99 "save\0" \ 100 "" 101 102#define CONFIG_PRAM 512 /* 512 KB */ 103 104#define CONFIG_SYS_LOAD_ADDR 0x00010000 105 106#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 107#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 108 109#define CONFIG_SYS_MBAR 0xF0000000 110#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 111#define CONFIG_SYS_INTSRAMSZ 0x8000 112 113/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 114 115/* 116 * Low Level Configuration Settings 117 * (address mappings, register initial values, etc.) 118 * You should know what you are doing if you make changes here. 119 */ 120/*----------------------------------------------------------------------- 121 * Definitions for initial stack pointer and data area (in DPRAM) 122 */ 123#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 124#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 125#define CONFIG_SYS_INIT_RAM_CTRL 0x21 126#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 127#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 128#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 129#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 130#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 131 132/*----------------------------------------------------------------------- 133 * Start addresses for the final memory configuration 134 * (Set up by the startup code) 135 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 136 */ 137#define CONFIG_SYS_SDRAM_BASE 0x00000000 138#define CONFIG_SYS_SDRAM_CFG1 0x73711630 139#define CONFIG_SYS_SDRAM_CFG2 0x46770000 140#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 141#define CONFIG_SYS_SDRAM_EMOD 0x40010000 142#define CONFIG_SYS_SDRAM_MODE 0x018D0000 143#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 144#ifdef CONFIG_SYS_DRAMSZ1 145# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 146#else 147# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 148#endif 149 150#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 151#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 152 153#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 154 155/* Reserve 256 kB for malloc() */ 156#define CONFIG_SYS_MALLOC_LEN (256 << 10) 157/* 158 * For booting Linux, the board info and command line data 159 * have to be in the first 8 MB of memory, since this is 160 * the maximum mapped by the Linux kernel during initialization ?? 161 */ 162#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 163 164/*----------------------------------------------------------------------- 165 * FLASH organization 166 */ 167#ifdef CONFIG_SYS_FLASH_CFI 168# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 169# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 170# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 171#ifdef CONFIG_SYS_NOR1SZ 172# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 173# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 174# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 175#else 176# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 178#endif 179#endif 180 181/* Configuration for environment 182 * Environment is not embedded in u-boot. First time runing may have env 183 * crc error warning if there is no correct environment on the flash. 184 */ 185 186/*----------------------------------------------------------------------- 187 * Cache Configuration 188 */ 189#define CONFIG_SYS_CACHELINE_SIZE 16 190 191#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 192 CONFIG_SYS_INIT_RAM_SIZE - 8) 193#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 194 CONFIG_SYS_INIT_RAM_SIZE - 4) 195#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 196 CF_CACR_IDCM) 197#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 198#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 199 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 200 CF_ACR_EN | CF_ACR_SM_ALL) 201#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 202 CF_CACR_IEC | CF_CACR_ICINVA) 203#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 204 CF_CACR_DEC | CF_CACR_DDCM_P | \ 205 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 206 207/*----------------------------------------------------------------------- 208 * Chipselect bank definitions 209 */ 210/* 211 * CS0 - NOR Flash 1, 2, 4, or 8MB 212 * CS1 - NOR Flash 213 * CS2 - Available 214 * CS3 - Available 215 * CS4 - Available 216 * CS5 - Available 217 */ 218#define CONFIG_SYS_CS0_BASE 0xFF800000 219#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 220#define CONFIG_SYS_CS0_CTRL 0x00101980 221 222#ifdef CONFIG_SYS_NOR1SZ 223#define CONFIG_SYS_CS1_BASE 0xE0000000 224#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 225#define CONFIG_SYS_CS1_CTRL 0x00101D80 226#endif 227 228#endif /* _M5485EVB_H */ 229