uboot/include/configs/MPC837XEMDS.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4 * Dave Liu <daveliu@freescale.com>
   5 */
   6
   7#ifndef __CONFIG_H
   8#define __CONFIG_H
   9
  10/*
  11 * High Level Configuration Options
  12 */
  13#define CONFIG_E300             1 /* E300 family */
  14
  15/*
  16 * IP blocks clock configuration
  17 */
  18#define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  19#define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  20#define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
  21
  22/*
  23 * System IO Config
  24 */
  25#define CONFIG_SYS_SICRH                0x00000000
  26#define CONFIG_SYS_SICRL                0x00000000
  27
  28/*
  29 * Output Buffer Impedance
  30 */
  31#define CONFIG_SYS_OBIR         0x31100000
  32
  33#define CONFIG_HWCONFIG
  34
  35/*
  36 * DDR Setup
  37 */
  38#define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  39#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  40#define CONFIG_SYS_83XX_DDR_USES_CS0
  41#define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
  42                                        | DDRCDR_ODT \
  43                                        | DDRCDR_Q_DRN)
  44                                        /* 0x80080001 */ /* ODT 150ohm on SoC */
  45
  46#undef CONFIG_DDR_ECC           /* support DDR ECC function */
  47#undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
  48
  49#define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
  50#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  51
  52#if defined(CONFIG_SPD_EEPROM)
  53#define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
  54#else
  55/*
  56 * Manually set up DDR parameters
  57 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  58 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  59 */
  60#define CONFIG_SYS_DDR_SIZE             512 /* MB */
  61#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  62#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  63                        | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
  64                        | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
  65                        | CSCONFIG_ROW_BIT_14 \
  66                        | CSCONFIG_COL_BIT_10)
  67                        /* 0x80010202 */
  68#define CONFIG_SYS_DDR_TIMING_3 0x00000000
  69#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  70                                | (0 << TIMING_CFG0_WRT_SHIFT) \
  71                                | (0 << TIMING_CFG0_RRT_SHIFT) \
  72                                | (0 << TIMING_CFG0_WWT_SHIFT) \
  73                                | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  74                                | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  75                                | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  76                                | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  77                                /* 0x00620802 */
  78#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  79                                | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  80                                | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  81                                | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  82                                | (13 << TIMING_CFG1_REFREC_SHIFT) \
  83                                | (3 << TIMING_CFG1_WRREC_SHIFT) \
  84                                | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  85                                | (2 << TIMING_CFG1_WRTORD_SHIFT))
  86                                /* 0x3935d322 */
  87#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  88                                | (6 << TIMING_CFG2_CPO_SHIFT) \
  89                                | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  90                                | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  91                                | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  92                                | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  93                                | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  94                                /* 0x131088c8 */
  95#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
  96                                | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  97                                /* 0x03E00100 */
  98#define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  99#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 100#define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 101                                | (0x1432 << SDRAM_MODE_SD_SHIFT))
 102                                /* ODT 150ohm CL=3, AL=1 on SDRAM */
 103#define CONFIG_SYS_DDR_MODE2    0x00000000
 104#endif
 105
 106/*
 107 * Memory test
 108 */
 109#undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 110
 111/*
 112 * The reserved memory
 113 */
 114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 115
 116#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 117#define CONFIG_SYS_RAMBOOT
 118#else
 119#undef CONFIG_SYS_RAMBOOT
 120#endif
 121
 122/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 123#define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 124#define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 125
 126/*
 127 * Initial RAM Base Address Setup
 128 */
 129#define CONFIG_SYS_INIT_RAM_LOCK        1
 130#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 131#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 132#define CONFIG_SYS_GBL_DATA_OFFSET      \
 133                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 134
 135/*
 136 * FLASH on the Local Bus
 137 */
 138#define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 139#define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 140
 141
 142#define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 143#define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 144
 145#undef CONFIG_SYS_FLASH_CHECKSUM
 146#define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 147#define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 148
 149/*
 150 * BCSR on the Local Bus
 151 */
 152#define CONFIG_SYS_BCSR         0xF8000000
 153                                        /* Access window base at BCSR base */
 154
 155/*
 156 * NAND Flash on the Local Bus
 157 */
 158#define CONFIG_SYS_MAX_NAND_DEVICE      1
 159#define CONFIG_NAND_FSL_ELBC    1
 160
 161#define CONFIG_SYS_NAND_BASE    0xE0600000
 162
 163
 164/*
 165 * Serial Port
 166 */
 167#define CONFIG_SYS_NS16550_SERIAL
 168#define CONFIG_SYS_NS16550_REG_SIZE     1
 169#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 170
 171#define CONFIG_SYS_BAUDRATE_TABLE  \
 172                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 173
 174#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 175#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 176
 177/* I2C */
 178#define CONFIG_SYS_I2C
 179#define CONFIG_SYS_I2C_FSL
 180#define CONFIG_SYS_FSL_I2C_SPEED        400000
 181#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 182#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 183#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 184
 185/*
 186 * Config on-board RTC
 187 */
 188#define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 189#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 190
 191/*
 192 * General PCI
 193 * Addresses are mapped 1-1.
 194 */
 195#define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 196#define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 197#define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 198#define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 199#define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 200#define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 201#define CONFIG_SYS_PCI_IO_BASE          0x00000000
 202#define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 203#define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 204
 205#define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 206#define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 207#define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 208
 209#define CONFIG_SYS_PCIE1_BASE           0xA0000000
 210#define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 211#define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 212#define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 213#define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 214#define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 215#define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 216#define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 217#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 218
 219#define CONFIG_SYS_PCIE2_BASE           0xC0000000
 220#define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 221#define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 222#define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 223#define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 224#define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 225#define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 226#define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 227#define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 228
 229#ifdef CONFIG_PCI
 230#define CONFIG_PCI_INDIRECT_BRIDGE
 231#ifndef __ASSEMBLY__
 232extern int board_pci_host_broken(void);
 233#endif
 234#define CONFIG_PCIE
 235#define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 236
 237#define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 238#define CONFIG_USB_EHCI_FSL
 239#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 240
 241#undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 242#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 243#endif /* CONFIG_PCI */
 244
 245/*
 246 * TSEC
 247 */
 248#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 249#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 250#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 251#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 252
 253/*
 254 * TSEC ethernet configuration
 255 */
 256#define CONFIG_TSEC1            1
 257#define CONFIG_TSEC1_NAME       "eTSEC0"
 258#define CONFIG_TSEC2            1
 259#define CONFIG_TSEC2_NAME       "eTSEC1"
 260#define TSEC1_PHY_ADDR          2
 261#define TSEC2_PHY_ADDR          3
 262#define TSEC1_PHY_ADDR_SGMII    8
 263#define TSEC2_PHY_ADDR_SGMII    4
 264#define TSEC1_PHYIDX            0
 265#define TSEC2_PHYIDX            0
 266#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 267#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 268
 269/* Options are: TSEC[0-1] */
 270#define CONFIG_ETHPRIME         "eTSEC1"
 271
 272/* SERDES */
 273#define CONFIG_FSL_SERDES
 274#define CONFIG_FSL_SERDES1      0xe3000
 275#define CONFIG_FSL_SERDES2      0xe3100
 276
 277/*
 278 * SATA
 279 */
 280#define CONFIG_SYS_SATA_MAX_DEVICE      2
 281#define CONFIG_SATA1
 282#define CONFIG_SYS_SATA1_OFFSET 0x18000
 283#define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 284#define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 285#define CONFIG_SATA2
 286#define CONFIG_SYS_SATA2_OFFSET 0x19000
 287#define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 288#define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 289
 290#ifdef CONFIG_FSL_SATA
 291#define CONFIG_LBA48
 292#endif
 293
 294/*
 295 * Environment
 296 */
 297
 298#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 299#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 300
 301/*
 302 * BOOTP options
 303 */
 304#define CONFIG_BOOTP_BOOTFILESIZE
 305
 306#undef CONFIG_WATCHDOG          /* watchdog disabled */
 307
 308#ifdef CONFIG_MMC
 309#define CONFIG_FSL_ESDHC_PIN_MUX
 310#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 311#endif
 312
 313/*
 314 * Miscellaneous configurable options
 315 */
 316#define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 317
 318/*
 319 * For booting Linux, the board info and command line data
 320 * have to be in the first 256 MB of memory, since this is
 321 * the maximum mapped by the Linux kernel during initialization.
 322 */
 323#define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 324#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 325
 326#if defined(CONFIG_CMD_KGDB)
 327#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 328#endif
 329
 330/*
 331 * Environment Configuration
 332 */
 333
 334#if defined(CONFIG_TSEC_ENET)
 335#define CONFIG_HAS_ETH0
 336#define CONFIG_HAS_ETH1
 337#endif
 338
 339#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 340
 341#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 342        "netdev=eth0\0"                                                 \
 343        "consoledev=ttyS0\0"                                            \
 344        "ramdiskaddr=1000000\0"                                         \
 345        "ramdiskfile=ramfs.83xx\0"                                      \
 346        "fdtaddr=780000\0"                                              \
 347        "fdtfile=mpc8379_mds.dtb\0"                                     \
 348        ""
 349
 350#define CONFIG_NFSBOOTCOMMAND                                           \
 351        "setenv bootargs root=/dev/nfs rw "                             \
 352                "nfsroot=$serverip:$rootpath "                          \
 353                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 354                                                        "$netdev:off "  \
 355                "console=$consoledev,$baudrate $othbootargs;"           \
 356        "tftp $loadaddr $bootfile;"                                     \
 357        "tftp $fdtaddr $fdtfile;"                                       \
 358        "bootm $loadaddr - $fdtaddr"
 359
 360#define CONFIG_RAMBOOTCOMMAND                                           \
 361        "setenv bootargs root=/dev/ram rw "                             \
 362                "console=$consoledev,$baudrate $othbootargs;"           \
 363        "tftp $ramdiskaddr $ramdiskfile;"                               \
 364        "tftp $loadaddr $bootfile;"                                     \
 365        "tftp $fdtaddr $fdtfile;"                                       \
 366        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 367
 368#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 369
 370#endif  /* __CONFIG_H */
 371