1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Toradex Colibri PXA270 configuration file 4 * 5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 6 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> 7 */ 8 9#ifndef __CONFIG_H 10#define __CONFIG_H 11 12/* 13 * High Level Board Configuration Options 14 */ 15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16/* Avoid overwriting factory configuration block */ 17#define CONFIG_BOARD_SIZE_LIMIT 0x40000 18 19/* 20 * Environment settings 21 */ 22#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 23#define CONFIG_BOOTCOMMAND \ 24 "if fatload mmc 0 0xa0000000 uImage; then " \ 25 "bootm 0xa0000000; " \ 26 "fi; " \ 27 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 28 "bootm 0xa0000000; " \ 29 "fi; " \ 30 "bootm 0xc0000;" 31#define CONFIG_TIMESTAMP 32#define CONFIG_CMDLINE_TAG 33#define CONFIG_SETUP_MEMORY_TAGS 34 35/* 36 * Serial Console Configuration 37 */ 38 39/* 40 * Bootloader Components Configuration 41 */ 42 43/* I2C support */ 44#ifdef CONFIG_SYS_I2C 45#define CONFIG_SYS_I2C_PXA 46#define CONFIG_PXA_STD_I2C 47#define CONFIG_PXA_PWR_I2C 48#define CONFIG_SYS_I2C_SPEED 100000 49#endif 50 51/* LCD support */ 52#ifdef CONFIG_LCD 53#define CONFIG_PXA_LCD 54#define CONFIG_PXA_VGA 55#define CONFIG_LCD_LOGO 56#endif 57 58/* 59 * Networking Configuration 60 */ 61#ifdef CONFIG_CMD_NET 62 63#define CONFIG_DRIVER_DM9000 1 64#define CONFIG_DM9000_BASE 0x08000000 65#define DM9000_IO (CONFIG_DM9000_BASE) 66#define DM9000_DATA (CONFIG_DM9000_BASE + 4) 67#define CONFIG_NET_RETRY_COUNT 10 68 69#define CONFIG_BOOTP_BOOTFILESIZE 70#endif 71 72/* 73 * Clock Configuration 74 */ 75#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 76 77/* 78 * DRAM Map 79 */ 80#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 81#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 82 83#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 84#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 85 86#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 87#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 88#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 89 90/* 91 * NOR FLASH 92 */ 93#ifdef CONFIG_CMD_FLASH 94#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 95#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 96#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 97 98#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 99 100#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 101#define CONFIG_SYS_MAX_FLASH_BANKS 1 102 103#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 104#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 105#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) 106#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) 107#endif 108 109#define CONFIG_SYS_MONITOR_BASE 0x0 110#define CONFIG_SYS_MONITOR_LEN 0x40000 111 112/* Skip factory configuration block */ 113 114/* 115 * GPIO settings 116 */ 117#define CONFIG_SYS_GPSR0_VAL 0x00000000 118#define CONFIG_SYS_GPSR1_VAL 0x00020000 119#define CONFIG_SYS_GPSR2_VAL 0x0002c000 120#define CONFIG_SYS_GPSR3_VAL 0x00000000 121 122#define CONFIG_SYS_GPCR0_VAL 0x00000000 123#define CONFIG_SYS_GPCR1_VAL 0x00000000 124#define CONFIG_SYS_GPCR2_VAL 0x00000000 125#define CONFIG_SYS_GPCR3_VAL 0x00000000 126 127#define CONFIG_SYS_GPDR0_VAL 0xc8008000 128#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 129#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff 130#define CONFIG_SYS_GPDR3_VAL 0x0061e804 131 132#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 133#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 134#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 135#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 136#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 137#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 138#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 139#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 140 141#define CONFIG_SYS_PSSR_VAL 0x30 142 143/* 144 * Clock settings 145 */ 146#define CONFIG_SYS_CKEN 0x00500240 147#define CONFIG_SYS_CCCR 0x02000290 148 149/* 150 * Memory settings 151 */ 152#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 153#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 154#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 155#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 156#define CONFIG_SYS_MDREFR_VAL 0x2003a031 157#define CONFIG_SYS_MDMRS_VAL 0x00220022 158#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 159#define CONFIG_SYS_SXCNFG_VAL 0x40044004 160 161/* 162 * PCMCIA and CF Interfaces 163 */ 164#define CONFIG_SYS_MECR_VAL 0x00000000 165#define CONFIG_SYS_MCMEM0_VAL 0x00028307 166#define CONFIG_SYS_MCMEM1_VAL 0x00014307 167#define CONFIG_SYS_MCATT0_VAL 0x00038787 168#define CONFIG_SYS_MCATT1_VAL 0x0001c787 169#define CONFIG_SYS_MCIO0_VAL 0x0002830f 170#define CONFIG_SYS_MCIO1_VAL 0x0001430f 171 172#include "pxa-common.h" 173 174#endif /* __CONFIG_H */ 175