LXR uboot/include/configs/tegra114-common.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#ifndef _TEGRA114_COMMON_H_
   7#define _TEGRA114_COMMON_H_
   8#include "tegra-common.h"
   9
  10/*
  11 * NS16550 Configuration
  12 */
  13#define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  14
  15/*
  16 * Miscellaneous configurable options
  17 */
  18#define CONFIG_STACKBASE        0x83800000      /* 56MB */
  19
  20/*-----------------------------------------------------------------------
  21 * Physical Memory Map
  22 */
  23
  24/*
  25 * Memory layout for where various images get loaded by boot scripts:
  26 *
  27 * scriptaddr can be pretty much anywhere that doesn't conflict with something
  28 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  29 *
  30 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  31 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  32 *
  33 * kernel_addr_r must be within the first 128M of RAM in order for the
  34 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  35 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  36 *   should not overlap that area, or the kernel will have to copy itself
  37 *   somewhere else before decompression. Similarly, the address of any other
  38 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  39 *   this up to 32M allows for a sizable kernel to be decompressed below the
  40 *   compressed load address.
  41 *
  42 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
  43 *   the compressed kernel to be up to 32M too.
  44 *
  45 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  46 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  47 */
  48#define CONFIG_LOADADDR 0x81000000
  49#define MEM_LAYOUT_ENV_SETTINGS \
  50        "scriptaddr=0x90000000\0" \
  51        "pxefile_addr_r=0x90100000\0" \
  52        "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  53        "fdt_addr_r=0x83000000\0" \
  54        "ramdisk_addr_r=0x83100000\0"
  55
  56/* Defines for SPL */
  57#define CONFIG_SYS_SPL_MALLOC_START     0x80090000
  58#define CONFIG_SPL_STACK                0x800ffffc
  59
  60/* For USB EHCI controller */
  61#define CONFIG_EHCI_IS_TDI
  62#define CONFIG_USB_EHCI_TXFIFO_THRESH   0x10
  63
  64#endif /* _TEGRA114_COMMON_H_ */
  65