LXR uboot/arch/arm/cpu/armv8/fsl-layerscape/ls1028a

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2019 NXP
   4 */
   5
   6#include <common.h>
   7#include <asm/arch/fsl_serdes.h>
   8
   9struct serdes_config {
  10        u32 protocol;
  11        u8 lanes[SRDS_MAX_LANES];
  12        u8 rcw_lanes[SRDS_MAX_LANES];
  13};
  14
  15static struct serdes_config serdes1_cfg_tbl[] = {
  16        /* SerDes 1 */
  17        {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
  18        {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
  19        {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
  20        {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
  21        {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
  22        {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
  23        {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
  24        {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
  25        {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
  26        {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
  27        {0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
  28        {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
  29        {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
  30        {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
  31        {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
  32        {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
  33        {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
  34        {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
  35        {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
  36        {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
  37        {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
  38        {0x7777, {SGMII1, SGMII2, SGMII3, SGMII4} },
  39        {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
  40        {0xb998, {SGMII_T1, SGMII2, SGMII3, PCIE1} },
  41        {0xbb56, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
  42        {}
  43};
  44
  45static struct serdes_config *serdes_cfg_tbl[] = {
  46        serdes1_cfg_tbl,
  47};
  48
  49enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  50{
  51        struct serdes_config *ptr;
  52
  53        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  54                return 0;
  55
  56        ptr = serdes_cfg_tbl[serdes];
  57        while (ptr->protocol) {
  58                if (ptr->protocol == cfg)
  59                        return ptr->lanes[lane];
  60                ptr++;
  61        }
  62
  63        return 0;
  64}
  65
  66int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  67{
  68        int i;
  69        struct serdes_config *ptr;
  70
  71        if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  72                return 0;
  73
  74        ptr = serdes_cfg_tbl[serdes];
  75        while (ptr->protocol) {
  76                if (ptr->protocol == prtcl)
  77                        break;
  78                ptr++;
  79        }
  80
  81        if (!ptr->protocol)
  82                return 0;
  83
  84        for (i = 0; i < SRDS_MAX_LANES; i++) {
  85                if (ptr->lanes[i] != NONE)
  86                        return 1;
  87        }
  88
  89        return 0;
  90}
  91