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6#ifndef _FSL_ICID_H_
7#define _FSL_ICID_H_
8
9#include <asm/types.h>
10#include <fsl_qbman.h>
11#include <fsl_sec.h>
12#include <asm/armv8/sec_firmware.h>
13
14struct icid_id_table {
15 const char *compat;
16 u32 id;
17 u32 reg;
18 phys_addr_t compat_addr;
19 phys_addr_t reg_addr;
20 bool le;
21};
22
23struct fman_icid_id_table {
24 u32 port_id;
25 u32 icid;
26};
27
28u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
29int fdt_get_smmu_phandle(void *blob);
30int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
31void set_icids(void);
32void fdt_fixup_icid(void *blob);
33
34#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
35 { .compat = name, \
36 .id = idA, \
37 .reg = regA, \
38 .compat_addr = compataddr, \
39 .reg_addr = addr, \
40 .le = _le \
41 }
42
43#ifdef CONFIG_SYS_FSL_SEC_LE
44#define SEC_IS_LE true
45#elif defined(CONFIG_SYS_FSL_SEC_BE)
46#define SEC_IS_LE false
47#endif
48
49#ifdef CONFIG_FSL_LSCH2
50
51#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
52#define SCFG_IS_LE true
53#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
54#define SCFG_IS_LE false
55#endif
56
57#define QDMA_IS_LE false
58
59#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
60 SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
61 offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
62 compataddr, SCFG_IS_LE)
63
64#define SET_USB_ICID(usb_num, compat, streamid) \
65 SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
66 CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
67
68#define SET_SATA_ICID(compat, streamid) \
69 SET_SCFG_ICID(compat, streamid, sata_icid,\
70 AHCI_BASE_ADDR)
71
72#define SET_SDHC_ICID(streamid) \
73 SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
74 CONFIG_SYS_FSL_ESDHC_ADDR)
75
76#define SET_EDMA_ICID(streamid) \
77 SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
78 EDMA_BASE_ADDR)
79
80#define SET_ETR_ICID(streamid) \
81 SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
82
83#define SET_DEBUG_ICID(streamid) \
84 SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
85
86#define SET_QE_ICID(streamid) \
87 SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
88 QE_BASE_ADDR)
89
90#define SET_QMAN_ICID(streamid) \
91 SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
92 offsetof(struct ccsr_qman, liodnr) + \
93 CONFIG_SYS_FSL_QMAN_ADDR, \
94 CONFIG_SYS_FSL_QMAN_ADDR, false)
95
96#define SET_BMAN_ICID(streamid) \
97 SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
98 offsetof(struct ccsr_bman, liodnr) + \
99 CONFIG_SYS_FSL_BMAN_ADDR, \
100 CONFIG_SYS_FSL_BMAN_ADDR, false)
101
102#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
103 { .port_id = (_port_id), .icid = (streamid) }
104
105#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
106
107#define SET_SEC_QI_ICID(streamid) \
108 SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
109 0, offsetof(ccsr_sec_t, qilcr_ls) + \
110 CONFIG_SYS_FSL_SEC_ADDR, \
111 CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
112
113extern struct fman_icid_id_table fman_icid_tbl[];
114extern int fman_icid_tbl_sz;
115
116#else
117
118#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
119#define GUR_IS_LE true
120#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
121#define GUR_IS_LE false
122#endif
123
124#define QDMA_IS_LE true
125
126#define SET_GUR_ICID(compat, streamid, name, compataddr) \
127 SET_ICID_ENTRY(compat, streamid, streamid, \
128 offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
129 compataddr, GUR_IS_LE)
130
131#define SET_USB_ICID(usb_num, compat, streamid) \
132 SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
133 CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
134
135#define SET_SATA_ICID(sata_num, compat, streamid) \
136 SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
137 AHCI_BASE_ADDR##sata_num)
138
139#define SET_SDHC_ICID(sdhc_num, streamid) \
140 SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
141 FSL_ESDHC##sdhc_num##_BASE_ADDR)
142
143#define SET_EDMA_ICID(streamid) \
144 SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
145 EDMA_BASE_ADDR)
146
147#define SET_GPU_ICID(compat, streamid) \
148 SET_GUR_ICID(compat, streamid, misc1_amqr,\
149 GPU_BASE_ADDR)
150
151#define SET_DISPLAY_ICID(streamid) \
152 SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
153 DISPLAY_BASE_ADDR)
154
155#define SEC_ICID_REG_VAL(streamid) (streamid)
156
157#endif
158
159#define SET_QDMA_ICID(compat, streamid) \
160 SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
161 QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
162 QDMA_BASE_ADDR, QDMA_IS_LE), \
163 SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
164 QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
165 QDMA_BASE_ADDR, QDMA_IS_LE)
166
167#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
168 SET_ICID_ENTRY( \
169 (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
170 (FSL_SEC_JR##jr_num##_OFFSET == \
171 SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
172 ? NULL \
173 : "fsl,sec-v4.0-job-ring"), \
174 streamid, \
175 SEC_ICID_REG_VAL(streamid), \
176 offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
177 CONFIG_SYS_FSL_SEC_ADDR, \
178 FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
179
180#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
181 SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
182 offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
183 CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
184
185#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
186 SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
187 offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
188 CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
189
190extern struct icid_id_table icid_tbl[];
191extern int icid_tbl_sz;
192
193#endif
194
