1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * DDR controller registers of the i.MX7 architecture 4 * 5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com 6 * 7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il> 8 */ 9 10#ifndef __ASM_ARCH_MX7_DDR_H__ 11#define __ASM_ARCH_MX7_DDR_H__ 12 13#ifndef __ASSEMBLY__ 14#include <linux/bitops.h> 15#endif 16 17/* DDRC Registers (DDRC_IPS_BASE_ADDR) */ 18struct ddrc { 19 u32 mstr; /* 0x0000 */ 20 u32 reserved1[0x18]; 21 u32 rfshtmg; /* 0x0064 */ 22 u32 reserved2[0x1a]; 23 u32 init0; /* 0x00d0 */ 24 u32 init1; /* 0x00d4 */ 25 u32 reserved3; 26 u32 init3; /* 0x00dc */ 27 u32 init4; /* 0x00e0 */ 28 u32 init5; /* 0x00e4 */ 29 u32 reserved4[0x03]; 30 u32 rankctl; /* 0x00f4 */ 31 u32 reserved5[0x02]; 32 u32 dramtmg0; /* 0x0100 */ 33 u32 dramtmg1; /* 0x0104 */ 34 u32 dramtmg2; /* 0x0108 */ 35 u32 dramtmg3; /* 0x010c */ 36 u32 dramtmg4; /* 0x0110 */ 37 u32 dramtmg5; /* 0x0114 */ 38 u32 reserved6[0x02]; 39 u32 dramtmg8; /* 0x0120 */ 40 u32 reserved7[0x17]; 41 u32 zqctl0; /* 0x0180 */ 42 u32 zqctl1; /* 0x0184 */ 43 u32 zqctl2; /* 0x0188 */ 44 u32 zqstat; /* 0x018c */ 45 u32 dfitmg0; /* 0x0190 */ 46 u32 dfitmg1; /* 0x0194 */ 47 u32 reserved9[0x02]; 48 u32 dfiupd0; /* 0x01a0 */ 49 u32 dfiupd1; /* 0x01a4 */ 50 u32 dfiupd2; /* 0x01a8 */ 51 u32 reserved10[0x15]; 52 u32 addrmap0; /* 0x0200 */ 53 u32 addrmap1; /* 0x0204 */ 54 u32 addrmap2; /* 0x0208 */ 55 u32 addrmap3; /* 0x020c */ 56 u32 addrmap4; /* 0x0210 */ 57 u32 addrmap5; /* 0x0214 */ 58 u32 addrmap6; /* 0x0218 */ 59 u32 reserved12[0x09]; 60 u32 odtcfg; /* 0x0240 */ 61 u32 odtmap; /* 0x0244 */ 62}; 63 64/* DDRC_MSTR fields */ 65#define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12 66#define MSTR_DATA_BUS_WIDTH_SHIFT 12 67#define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24 68#define MSTR_DATA_ACTIVE_RANKS_SHIFT 24 69/* DDRC_ADDRMAP1 fields */ 70#define ADDRMAP1_BANK_B0_MASK 0x1f << 0 71#define ADDRMAP1_BANK_B0_SHIFT 0 72#define ADDRMAP1_BANK_B1_MASK 0x1f << 8 73#define ADDRMAP1_BANK_B1_SHIFT 8 74#define ADDRMAP1_BANK_B2_MASK 0x1f << 16 75#define ADDRMAP1_BANK_B2_SHIFT 16 76/* DDRC_ADDRMAP2 fields */ 77#define ADDRMAP2_COL_B2_MASK 0xF << 0 78#define ADDRMAP2_COL_B2_SHIFT 0 79#define ADDRMAP2_COL_B3_MASK 0xF << 8 80#define ADDRMAP2_COL_B3_SHIFT 8 81#define ADDRMAP2_COL_B4_MASK 0xF << 16 82#define ADDRMAP2_COL_B4_SHIFT 16 83#define ADDRMAP2_COL_B5_MASK 0xF << 24 84#define ADDRMAP2_COL_B5_SHIFT 24 85/* DDRC_ADDRMAP3 fields */ 86#define ADDRMAP3_COL_B6_MASK 0xF << 0 87#define ADDRMAP3_COL_B6_SHIFT 0 88#define ADDRMAP3_COL_B7_MASK 0xF << 8 89#define ADDRMAP3_COL_B7_SHIFT 8 90#define ADDRMAP3_COL_B8_MASK 0xF << 16 91#define ADDRMAP3_COL_B8_SHIFT 16 92#define ADDRMAP3_COL_B9_MASK 0xF << 24 93#define ADDRMAP3_COL_B9_SHIFT 24 94/* DDRC_ADDRMAP4 fields */ 95#define ADDRMAP4_COL_B10_MASK 0xF << 0 96#define ADDRMAP4_COL_B10_SHIFT 0 97#define ADDRMAP4_COL_B11_MASK 0xF << 8 98#define ADDRMAP4_COL_B11_SHIFT 8 99/* DDRC_ADDRMAP5 fields */ 100#define ADDRMAP5_ROW_B0_MASK 0xF << 0 101#define ADDRMAP5_ROW_B0_SHIFT 0 102#define ADDRMAP5_ROW_B1_MASK 0xF << 8 103#define ADDRMAP5_ROW_B1_SHIFT 8 104#define ADDRMAP5_ROW_B2_10_MASK 0xF << 16 105#define ADDRMAP5_ROW_B2_10_SHIFT 16 106#define ADDRMAP5_ROW_B11_MASK 0xF << 24 107#define ADDRMAP5_ROW_B11_SHIFT 24 108/* DDRC_ADDRMAP6 fields */ 109#define ADDRMAP6_ROW_B12_MASK 0xF << 0 110#define ADDRMAP6_ROW_B12_SHIFT 0 111#define ADDRMAP6_ROW_B13_MASK 0xF << 8 112#define ADDRMAP6_ROW_B13_SHIFT 8 113#define ADDRMAP6_ROW_B14_MASK 0xF << 16 114#define ADDRMAP6_ROW_B14_SHIFT 16 115#define ADDRMAP6_ROW_B15_MASK 0xF << 24 116#define ADDRMAP6_ROW_B15_SHIFT 24 117 118/* DDRC_MP Registers */ 119#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc) 120struct ddrc_mp { 121 u32 reserved1[0x25]; 122 u32 pctrl_0; /* 0x0094 */ 123}; 124 125/* DDR_PHY registers */ 126struct ddr_phy { 127 u32 phy_con0; /* 0x0000 */ 128 u32 phy_con1; /* 0x0004 */ 129 u32 reserved1[0x02]; 130 u32 phy_con4; /* 0x0010 */ 131 u32 reserved2; 132 u32 offset_lp_con0; /* 0x0018 */ 133 u32 reserved3; 134 u32 offset_rd_con0; /* 0x0020 */ 135 u32 reserved4[0x03]; 136 u32 offset_wr_con0; /* 0x0030 */ 137 u32 reserved5[0x07]; 138 u32 cmd_sdll_con0; /* 0x0050 */ 139 u32 reserved6[0x06]; 140 u32 cmd_lvl_con0; /* 0x006c */ 141 u32 reserved7[0x02]; 142 u32 cmd_lvl_con3; /* 0x0078 */ 143 u32 cmd_deskew_con0; /* 0x007c */ 144 u32 cmd_deskew_con1; /* 0x0080 */ 145 u32 cmd_deskew_con2; /* 0x0084 */ 146 u32 cmd_deskew_con3; /* 0x0088 */ 147 u32 reserved8[0x02]; 148 u32 cmd_deskew_con4; /* 0x0094 */ 149 u32 reserved9; 150 u32 drvds_con0; /* 0x009c */ 151 u32 reserved10[0x04]; 152 u32 mdll_con0; /* 0x00b0 */ 153 u32 reserved11[0x03]; 154 u32 zq_con0; /* 0x00c0 */ 155}; 156 157#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24) 158 159#define MX7_CAL_VAL_MAX 5 160/* Calibration parameters */ 161struct mx7_calibration { 162 int num_val; /* Number of calibration values */ 163 u32 values[MX7_CAL_VAL_MAX]; /* calibration values */ 164}; 165 166void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, 167 struct ddr_phy *ddr_phy_regs_val, 168 struct mx7_calibration *calib_param); 169 170#endif /*__ASM_ARCH_MX7_DDR_H__ */ 171