LXR uboot/arch/arm/mach-davinci/cpu.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2004 Texas Instruments.
   4 * Copyright (C) 2009 David Brownell
   5 */
   6
   7#include <common.h>
   8#include <init.h>
   9#include <asm/arch/hardware.h>
  10#include <asm/io.h>
  11
  12DECLARE_GLOBAL_DATA_PTR;
  13
  14/* offsets from PLL controller base */
  15#define PLLC_PLLCTL     0x100
  16#define PLLC_PLLM       0x110
  17#define PLLC_PREDIV     0x114
  18#define PLLC_PLLDIV1    0x118
  19#define PLLC_PLLDIV2    0x11c
  20#define PLLC_PLLDIV3    0x120
  21#define PLLC_POSTDIV    0x128
  22#define PLLC_BPDIV      0x12c
  23#define PLLC_PLLDIV4    0x160
  24#define PLLC_PLLDIV5    0x164
  25#define PLLC_PLLDIV6    0x168
  26#define PLLC_PLLDIV7    0x16c
  27#define PLLC_PLLDIV8    0x170
  28#define PLLC_PLLDIV9    0x174
  29
  30unsigned int sysdiv[9] = {
  31        PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
  32        PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
  33};
  34
  35int clk_get(enum davinci_clk_ids id)
  36{
  37        int pre_div;
  38        int pllm;
  39        int post_div;
  40        int pll_out;
  41        unsigned int pll_base;
  42
  43        pll_out = CONFIG_SYS_OSCIN_FREQ;
  44
  45        if (id == DAVINCI_AUXCLK_CLKID)
  46                goto out;
  47
  48        if ((id >> 16) == 1)
  49                pll_base = (unsigned int)davinci_pllc1_regs;
  50        else
  51                pll_base = (unsigned int)davinci_pllc0_regs;
  52
  53        id &= 0xFFFF;
  54
  55        /*
  56         * Lets keep this simple. Combining operations can result in
  57         * unexpected approximations
  58         */
  59        pre_div = (readl(pll_base + PLLC_PREDIV) &
  60                DAVINCI_PLLC_DIV_MASK) + 1;
  61        pllm = readl(pll_base + PLLC_PLLM) + 1;
  62
  63        pll_out /= pre_div;
  64        pll_out *= pllm;
  65
  66        if (id == DAVINCI_PLLM_CLKID)
  67                goto out;
  68
  69        post_div = (readl(pll_base + PLLC_POSTDIV) &
  70                DAVINCI_PLLC_DIV_MASK) + 1;
  71
  72        pll_out /= post_div;
  73
  74        if (id == DAVINCI_PLLC_CLKID)
  75                goto out;
  76
  77        pll_out /= (readl(pll_base + sysdiv[id - 1]) &
  78                DAVINCI_PLLC_DIV_MASK) + 1;
  79
  80out:
  81        return pll_out;
  82}
  83
  84int set_cpu_clk_info(void)
  85{
  86        gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
  87        /* DDR PHY uses an x2 input clock */
  88        gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
  89                                (clk_get(DAVINCI_DDR_CLKID) / 1000000);
  90        gd->bd->bi_dsp_freq = 0;
  91        return 0;
  92}
  93