1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * MIPS Coherence Manager (CM) Register Definitions 4 * 5 * Copyright (c) 2016 Imagination Technologies Ltd. 6 */ 7#ifndef __MIPS_ASM_CM_H__ 8#define __MIPS_ASM_CM_H__ 9 10/* Global Control Register (GCR) offsets */ 11#define GCR_BASE 0x0008 12#define GCR_BASE_UPPER 0x000c 13#define GCR_REV 0x0030 14#define GCR_L2_CONFIG 0x0130 15#define GCR_L2_TAG_ADDR 0x0600 16#define GCR_L2_TAG_ADDR_UPPER 0x0604 17#define GCR_L2_TAG_STATE 0x0608 18#define GCR_L2_TAG_STATE_UPPER 0x060c 19#define GCR_L2_DATA 0x0610 20#define GCR_L2_DATA_UPPER 0x0614 21#define GCR_Cx_COHERENCE 0x2008 22 23/* GCR_REV CM versions */ 24#define GCR_REV_CM3 0x0800 25 26/* GCR_L2_CONFIG fields */ 27#define GCR_L2_CONFIG_ASSOC_SHIFT 0 28#define GCR_L2_CONFIG_ASSOC_BITS 8 29#define GCR_L2_CONFIG_LINESZ_SHIFT 8 30#define GCR_L2_CONFIG_LINESZ_BITS 4 31#define GCR_L2_CONFIG_SETSZ_SHIFT 12 32#define GCR_L2_CONFIG_SETSZ_BITS 4 33#define GCR_L2_CONFIG_BYPASS (1 << 20) 34 35/* GCR_Cx_COHERENCE */ 36#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) 37#define GCR_Cx_COHERENCE_EN (0x1 << 0) 38 39#ifndef __ASSEMBLY__ 40 41#include <asm/io.h> 42#include <linux/bitops.h> 43 44#if CONFIG_IS_ENABLED(MIPS_CM) 45static inline void *mips_cm_base(void) 46{ 47 return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 48} 49 50static inline unsigned long mips_cm_l2_line_size(void) 51{ 52 unsigned long l2conf, line_sz; 53 54 l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 55 56 line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 57 line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 58 return line_sz ? (2 << line_sz) : 0; 59} 60#else 61static inline void *mips_cm_base(void) 62{ 63 return NULL; 64} 65 66static inline unsigned long mips_cm_l2_line_size(void) 67{ 68 return 0; 69} 70#endif 71 72#endif /* !__ASSEMBLY__ */ 73 74#endif /* __MIPS_ASM_CM_H__ */ 75