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19#include <common.h>
20#include <cpu_func.h>
21#include <net.h>
22#include <time.h>
23#include <vsprintf.h>
24#include <watchdog.h>
25#include <command.h>
26#include <mpc8xx.h>
27#include <netdev.h>
28#include <asm/cache.h>
29#include <asm/cpm_8xx.h>
30#include <linux/compiler.h>
31#include <asm/io.h>
32
33#if defined(CONFIG_OF_LIBFDT)
34#include <linux/libfdt.h>
35#include <fdt_support.h>
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
40
41
42
43int checkicache(void)
44{
45 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
46 memctl8xx_t __iomem *memctl = &immap->im_memctl;
47 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
48
49 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
50 u32 m;
51 u32 lines = -1;
52
53 wr_ic_cst(IDC_UNALL);
54 wr_ic_cst(IDC_INVALL);
55 wr_ic_cst(IDC_DISABLE);
56 __asm__ volatile ("isync");
57
58 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
59 wr_ic_adr(k);
60 wr_ic_cst(IDC_LDLCK);
61 __asm__ volatile ("isync");
62
63 lines++;
64 k += 0x10;
65 }
66
67 wr_ic_cst(IDC_UNALL);
68 wr_ic_cst(IDC_INVALL);
69
70 if (cacheon)
71 wr_ic_cst(IDC_ENABLE);
72 else
73 wr_ic_cst(IDC_DISABLE);
74
75 __asm__ volatile ("isync");
76
77 return lines << 4;
78};
79
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81
82
83
84static int checkdcache(void)
85{
86 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
87 memctl8xx_t __iomem *memctl = &immap->im_memctl;
88 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
89
90 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
91 u32 m;
92 u32 lines = -1;
93
94 wr_dc_cst(IDC_UNALL);
95 wr_dc_cst(IDC_INVALL);
96 wr_dc_cst(IDC_DISABLE);
97
98 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
99 wr_dc_adr(k);
100 wr_dc_cst(IDC_LDLCK);
101 lines++;
102 k += 0x10;
103 }
104
105 wr_dc_cst(IDC_UNALL);
106 wr_dc_cst(IDC_INVALL);
107
108 if (cacheon)
109 wr_dc_cst(IDC_ENABLE);
110 else
111 wr_dc_cst(IDC_DISABLE);
112
113 return lines << 4;
114};
115
116static int check_CPU(long clock, uint pvr, uint immr)
117{
118 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
119 uint k;
120 char buf[32];
121
122
123
124 if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
125 return -1;
126
127 k = (immr << 16) |
128 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
129
130
131
132
133
134 switch (k) {
135
136 case 0x08010004:
137 printf("MPC866xxxZPnnA");
138 break;
139 case 0x08000003:
140 printf("MPC866xxxZPnn");
141 break;
142 case 0x09000000:
143 puts("MPC885ZPnn");
144 break;
145
146 default:
147 printf("unknown MPC86x (0x%08x)", k);
148 break;
149 }
150
151 printf(" at %s MHz: ", strmhz(buf, clock));
152
153 print_size(checkicache(), " I-Cache ");
154 print_size(checkdcache(), " D-Cache");
155
156
157
158 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
159 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
160 printf(" FEC present");
161
162 putc('\n');
163
164 return 0;
165}
166
167
168
169int checkcpu(void)
170{
171 ulong clock = gd->cpu_clk;
172 uint immr = get_immr();
173 uint pvr = get_pvr();
174
175 puts("CPU: ");
176
177 return check_CPU(clock, pvr, immr);
178}
179
180
181
182void upmconfig(uint upm, uint *table, uint size)
183{
184 uint i;
185 uint addr = 0;
186 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
187 memctl8xx_t __iomem *memctl = &immap->im_memctl;
188
189 for (i = 0; i < size; i++) {
190 out_be32(&memctl->memc_mdr, table[i]);
191 out_be32(&memctl->memc_mcr, addr | upm);
192 addr++;
193 }
194}
195
196
197
198int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
199{
200 ulong msr, addr;
201
202 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
203
204
205 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
206
207
208 __asm__ volatile ("mtspr 81, 0");
209 __asm__ volatile ("mfmsr %0" : "=r" (msr));
210
211 msr &= ~0x1030;
212 __asm__ volatile ("mtmsr %0" : : "r" (msr));
213
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216
217
218#ifdef CONFIG_SYS_RESET_ADDRESS
219 addr = CONFIG_SYS_RESET_ADDRESS;
220#else
221
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227
228 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
229#endif
230 ((void (*)(void)) addr)();
231 return 1;
232}
233
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240
241unsigned long get_tbclk(void)
242{
243 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
244 ulong oscclk, factor, pll;
245
246 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
247 return gd->cpu_clk / 16;
248
249 pll = in_be32(&immap->im_clkrst.car_plprcr);
250
251#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
252
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263
264 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
265 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
266
267 oscclk = gd->cpu_clk / factor;
268
269 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
270 factor > 2)
271 return oscclk / 4;
272
273 return oscclk / 16;
274}
275
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278
279
280int cpu_eth_init(struct bd_info *bis)
281{
282#if defined(CONFIG_MPC8XX_FEC)
283 fec_initialize(bis);
284#endif
285 return 0;
286}
287