1
2
3
4
5
6
7
8
9
10
11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
14#include <asm/types.h>
15#include <asm/fsl_dma.h>
16#include <asm/fsl_i2c.h>
17#include <fsl_ifc.h>
18#include <fsl_sec.h>
19#include <fsl_sfp.h>
20#include <asm/fsl_lbc.h>
21#include <fsl_fman.h>
22#include <fsl_immap.h>
23
24typedef struct ccsr_local {
25 u32 ccsrbarh;
26 u32 ccsrbarl;
27 u32 ccsrar;
28#define CCSRAR_C 0x80000000
29 u8 res1[4];
30 u32 altcbarh;
31 u32 altcbarl;
32 u32 altcar;
33 u8 res2[4];
34 u32 bstrh;
35 u32 bstrl;
36 u32 bstrar;
37 u8 res3[0xbd4];
38 struct {
39 u32 lawbarh;
40 u32 lawbarl;
41 u32 lawar;
42 u8 res4[4];
43 } law[32];
44 u8 res35[0x204];
45} ccsr_local_t;
46
47
48typedef struct ccsr_local_ecm {
49 u32 ccsrbar;
50 u8 res1[4];
51 u32 altcbar;
52 u8 res2[4];
53 u32 altcar;
54 u8 res3[12];
55 u32 bptr;
56 u8 res4[3044];
57 u32 lawbar0;
58 u8 res5[4];
59 u32 lawar0;
60 u8 res6[20];
61 u32 lawbar1;
62 u8 res7[4];
63 u32 lawar1;
64 u8 res8[20];
65 u32 lawbar2;
66 u8 res9[4];
67 u32 lawar2;
68 u8 res10[20];
69 u32 lawbar3;
70 u8 res11[4];
71 u32 lawar3;
72 u8 res12[20];
73 u32 lawbar4;
74 u8 res13[4];
75 u32 lawar4;
76 u8 res14[20];
77 u32 lawbar5;
78 u8 res15[4];
79 u32 lawar5;
80 u8 res16[20];
81 u32 lawbar6;
82 u8 res17[4];
83 u32 lawar6;
84 u8 res18[20];
85 u32 lawbar7;
86 u8 res19[4];
87 u32 lawar7;
88 u8 res19_8a[20];
89 u32 lawbar8;
90 u8 res19_8b[4];
91 u32 lawar8;
92 u8 res19_9a[20];
93 u32 lawbar9;
94 u8 res19_9b[4];
95 u32 lawar9;
96 u8 res19_10a[20];
97 u32 lawbar10;
98 u8 res19_10b[4];
99 u32 lawar10;
100 u8 res19_11a[20];
101 u32 lawbar11;
102 u8 res19_11b[4];
103 u32 lawar11;
104 u8 res20[652];
105 u32 eebacr;
106 u8 res21[12];
107 u32 eebpcr;
108 u8 res22[3564];
109 u32 eedr;
110 u8 res23[4];
111 u32 eeer;
112 u32 eeatr;
113 u32 eeadr;
114 u8 res24[492];
115} ccsr_local_ecm_t;
116
117#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000
118#define DDR_EOR_ADDR_HASH_EN 0x40000000
119
120
121typedef struct ccsr_i2c {
122 struct fsl_i2c_base i2c[1];
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
124} ccsr_i2c_t;
125
126#if defined(CONFIG_ARCH_MPC8540) || \
127 defined(CONFIG_ARCH_MPC8541) || \
128 defined(CONFIG_ARCH_MPC8548) || \
129 defined(CONFIG_ARCH_MPC8555)
130
131typedef struct ccsr_duart {
132 u8 res1[1280];
133
134 u8 urbr1_uthr1_udlb1;
135
136 u8 uier1_udmb1;
137
138 u8 uiir1_ufcr1_uafr1;
139 u8 ulcr1;
140 u8 umcr1;
141 u8 ulsr1;
142 u8 umsr1;
143 u8 uscr1;
144 u8 res2[8];
145 u8 udsr1;
146 u8 res3[239];
147
148 u8 urbr2_uthr2_udlb2;
149
150 u8 uier2_udmb2;
151
152 u8 uiir2_ufcr2_uafr2;
153 u8 ulcr2;
154 u8 umcr2;
155 u8 ulsr2;
156 u8 umsr2;
157 u8 uscr2;
158 u8 res4[8];
159 u8 udsr2;
160 u8 res5[2543];
161} ccsr_duart_t;
162#else
163typedef struct ccsr_duart {
164 u8 res[4096];
165} ccsr_duart_t;
166#endif
167
168
169typedef struct ccsr_espi {
170 u32 mode;
171 u32 event;
172 u32 mask;
173 u32 com;
174 u32 tx;
175 u32 rx;
176 u8 res1[8];
177 u32 csmode[4];
178 u8 res2[4048];
179} ccsr_espi_t;
180
181
182typedef struct ccsr_pcix {
183 u32 cfg_addr;
184 u32 cfg_data;
185 u32 int_ack;
186 u8 res000c[52];
187 u32 liodn_base;
188 u8 res0044[2996];
189 u32 ipver1;
190 u32 ipver2;
191 u32 potar0;
192 u32 potear0;
193 u32 powbar0;
194 u32 powbear0;
195 u32 powar0;
196 u8 res2[12];
197 u32 potar1;
198 u32 potear1;
199 u32 powbar1;
200 u32 powbear1;
201 u32 powar1;
202 u8 res3[12];
203 u32 potar2;
204 u32 potear2;
205 u32 powbar2;
206 u32 powbear2;
207 u32 powar2;
208 u8 res4[12];
209 u32 potar3;
210 u32 potear3;
211 u32 powbar3;
212 u32 powbear3;
213 u32 powar3;
214 u8 res5[12];
215 u32 potar4;
216 u32 potear4;
217 u32 powbar4;
218 u32 powbear4;
219 u32 powar4;
220 u8 res6[268];
221 u32 pitar3;
222 u32 pitear3;
223 u32 piwbar3;
224 u32 piwbear3;
225 u32 piwar3;
226 u8 res7[12];
227 u32 pitar2;
228 u32 pitear2;
229 u32 piwbar2;
230 u32 piwbear2;
231 u32 piwar2;
232 u8 res8[12];
233 u32 pitar1;
234 u32 pitear1;
235 u32 piwbar1;
236 u8 res9[4];
237 u32 piwar1;
238 u8 res10[12];
239 u32 pedr;
240 u32 pecdr;
241 u32 peer;
242 u32 peattrcr;
243 u32 peaddrcr;
244 u32 peextaddrcr;
245 u32 pedlcr;
246 u32 pedhcr;
247 u32 gas_timr;
248 u8 res11[476];
249} ccsr_pcix_t;
250
251#define PCIX_COMMAND 0x62
252#define POWAR_EN 0x80000000
253#define POWAR_IO_READ 0x00080000
254#define POWAR_MEM_READ 0x00040000
255#define POWAR_IO_WRITE 0x00008000
256#define POWAR_MEM_WRITE 0x00004000
257#define POWAR_MEM_512M 0x0000001c
258#define POWAR_IO_1M 0x00000013
259
260#define PIWAR_EN 0x80000000
261#define PIWAR_PF 0x20000000
262#define PIWAR_LOCAL 0x00f00000
263#define PIWAR_READ_SNOOP 0x00050000
264#define PIWAR_WRITE_SNOOP 0x00005000
265#define PIWAR_MEM_2G 0x0000001e
266
267#ifndef CONFIG_MPC85XX_GPIO
268typedef struct ccsr_gpio {
269 u32 gpdir;
270 u32 gpodr;
271 u32 gpdat;
272 u32 gpier;
273 u32 gpimr;
274 u32 gpicr;
275} ccsr_gpio_t;
276#endif
277
278
279typedef struct ccsr_l2cache {
280 u32 l2ctl;
281 u8 res1[12];
282 u32 l2cewar0;
283 u8 res2[4];
284 u32 l2cewcr0;
285 u8 res3[4];
286 u32 l2cewar1;
287 u8 res4[4];
288 u32 l2cewcr1;
289 u8 res5[4];
290 u32 l2cewar2;
291 u8 res6[4];
292 u32 l2cewcr2;
293 u8 res7[4];
294 u32 l2cewar3;
295 u8 res8[4];
296 u32 l2cewcr3;
297 u8 res9[180];
298 u32 l2srbar0;
299 u8 res10[4];
300 u32 l2srbar1;
301 u8 res11[3316];
302 u32 l2errinjhi;
303 u32 l2errinjlo;
304 u32 l2errinjctl;
305 u8 res12[20];
306 u32 l2captdatahi;
307 u32 l2captdatalo;
308 u32 l2captecc;
309 u8 res13[20];
310 u32 l2errdet;
311 u32 l2errdis;
312 u32 l2errinten;
313 u32 l2errattr;
314 u32 l2erraddr;
315 u8 res14[4];
316 u32 l2errctl;
317 u8 res15[420];
318} ccsr_l2cache_t;
319
320#define MPC85xx_L2CTL_L2E 0x80000000
321#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
322#define MPC85xx_L2ERRDIS_MBECC 0x00000008
323#define MPC85xx_L2ERRDIS_SBECC 0x00000004
324
325
326typedef struct ccsr_dma {
327 u8 res1[256];
328 struct fsl_dma dma[4];
329 u32 dgsr;
330 u8 res2[11516];
331} ccsr_dma_t;
332
333
334typedef struct ccsr_tsec {
335 u8 res1[16];
336 u32 ievent;
337 u32 imask;
338 u32 edis;
339 u8 res2[4];
340 u32 ecntrl;
341 u32 minflr;
342 u32 ptv;
343 u32 dmactrl;
344 u32 tbipa;
345 u8 res3[88];
346 u32 fifo_tx_thr;
347 u8 res4[8];
348 u32 fifo_tx_starve;
349 u32 fifo_tx_starve_shutoff;
350 u8 res5[96];
351 u32 tctrl;
352 u32 tstat;
353 u8 res6[4];
354 u32 tbdlen;
355 u8 res7[16];
356 u32 ctbptrh;
357 u32 ctbptr;
358 u8 res8[88];
359 u32 tbptrh;
360 u32 tbptr;
361 u8 res9[120];
362 u32 tbaseh;
363 u32 tbase;
364 u8 res10[168];
365 u32 ostbd;
366 u32 ostbdp;
367 u32 os32tbdp;
368 u32 os32iptrh;
369 u32 os32iptrl;
370 u32 os32tbdr;
371 u32 os32iil;
372 u8 res11[52];
373 u32 rctrl;
374 u32 rstat;
375 u8 res12[4];
376 u32 rbdlen;
377 u8 res13[16];
378 u32 crbptrh;
379 u32 crbptr;
380 u8 res14[24];
381 u32 mrblr;
382 u32 mrblr2r3;
383 u8 res15[56];
384 u32 rbptrh;
385 u32 rbptr;
386 u32 rbptrh1;
387 u32 rbptrl1;
388 u32 rbptrh2;
389 u32 rbptrl2;
390 u32 rbptrh3;
391 u32 rbptrl3;
392 u8 res16[96];
393 u32 rbaseh;
394 u32 rbase;
395 u32 rbaseh1;
396 u32 rbasel1;
397 u32 rbaseh2;
398 u32 rbasel2;
399 u32 rbaseh3;
400 u32 rbasel3;
401 u8 res17[224];
402 u32 maccfg1;
403 u32 maccfg2;
404 u32 ipgifg;
405 u32 hafdup;
406 u32 maxfrm;
407 u8 res18[12];
408 u32 miimcfg;
409 u32 miimcom;
410 u32 miimadd;
411 u32 miimcon;
412 u32 miimstat;
413 u32 miimind;
414 u8 res19[4];
415 u32 ifstat;
416 u32 macstnaddr1;
417 u32 macstnaddr2;
418 u8 res20[312];
419 u32 tr64;
420 u32 tr127;
421 u32 tr255;
422 u32 tr511;
423 u32 tr1k;
424 u32 trmax;
425 u32 trmgv;
426 u32 rbyt;
427 u32 rpkt;
428 u32 rfcs;
429 u32 rmca;
430 u32 rbca;
431 u32 rxcf;
432 u32 rxpf;
433 u32 rxuo;
434 u32 raln;
435 u32 rflr;
436 u32 rcde;
437 u32 rcse;
438 u32 rund;
439 u32 rovr;
440 u32 rfrg;
441 u32 rjbr;
442 u32 rdrp;
443 u32 tbyt;
444 u32 tpkt;
445 u32 tmca;
446 u32 tbca;
447 u32 txpf;
448 u32 tdfr;
449 u32 tedf;
450 u32 tscl;
451 u32 tmcl;
452 u32 tlcl;
453 u32 txcl;
454 u32 tncl;
455 u8 res21[4];
456 u32 tdrp;
457 u32 tjbr;
458 u32 tfcs;
459 u32 txcf;
460 u32 tovr;
461 u32 tund;
462 u32 tfrg;
463 u32 car1;
464 u32 car2;
465 u32 cam1;
466 u32 cam2;
467 u8 res22[192];
468 u32 iaddr0;
469 u32 iaddr1;
470 u32 iaddr2;
471 u32 iaddr3;
472 u32 iaddr4;
473 u32 iaddr5;
474 u32 iaddr6;
475 u32 iaddr7;
476 u8 res23[96];
477 u32 gaddr0;
478 u32 gaddr1;
479 u32 gaddr2;
480 u32 gaddr3;
481 u32 gaddr4;
482 u32 gaddr5;
483 u32 gaddr6;
484 u32 gaddr7;
485 u8 res24[96];
486 u32 pmd0;
487 u8 res25[4];
488 u32 pmask0;
489 u8 res26[4];
490 u32 pcntrl0;
491 u8 res27[4];
492 u32 pattrb0;
493 u32 pattrbeli0;
494 u32 pmd1;
495 u8 res28[4];
496 u32 pmask1;
497 u8 res29[4];
498 u32 pcntrl1;
499 u8 res30[4];
500 u32 pattrb1;
501 u32 pattrbeli1;
502 u32 pmd2;
503 u8 res31[4];
504 u32 pmask2;
505 u8 res32[4];
506 u32 pcntrl2;
507 u8 res33[4];
508 u32 pattrb2;
509 u32 pattrbeli2;
510 u32 pmd3;
511 u8 res34[4];
512 u32 pmask3;
513 u8 res35[4];
514 u32 pcntrl3;
515 u8 res36[4];
516 u32 pattrb3;
517 u32 pattrbeli3;
518 u32 pmd4;
519 u8 res37[4];
520 u32 pmask4;
521 u8 res38[4];
522 u32 pcntrl4;
523 u8 res39[4];
524 u32 pattrb4;
525 u32 pattrbeli4;
526 u32 pmd5;
527 u8 res40[4];
528 u32 pmask5;
529 u8 res41[4];
530 u32 pcntrl5;
531 u8 res42[4];
532 u32 pattrb5;
533 u32 pattrbeli5;
534 u32 pmd6;
535 u8 res43[4];
536 u32 pmask6;
537 u8 res44[4];
538 u32 pcntrl6;
539 u8 res45[4];
540 u32 pattrb6;
541 u32 pattrbeli6;
542 u32 pmd7;
543 u8 res46[4];
544 u32 pmask7;
545 u8 res47[4];
546 u32 pcntrl7;
547 u8 res48[4];
548 u32 pattrb7;
549 u32 pattrbeli7;
550 u32 pmd8;
551 u8 res49[4];
552 u32 pmask8;
553 u8 res50[4];
554 u32 pcntrl8;
555 u8 res51[4];
556 u32 pattrb8;
557 u32 pattrbeli8;
558 u32 pmd9;
559 u8 res52[4];
560 u32 pmask9;
561 u8 res53[4];
562 u32 pcntrl9;
563 u8 res54[4];
564 u32 pattrb9;
565 u32 pattrbeli9;
566 u32 pmd10;
567 u8 res55[4];
568 u32 pmask10;
569 u8 res56[4];
570 u32 pcntrl10;
571 u8 res57[4];
572 u32 pattrb10;
573 u32 pattrbeli10;
574 u32 pmd11;
575 u8 res58[4];
576 u32 pmask11;
577 u8 res59[4];
578 u32 pcntrl11;
579 u8 res60[4];
580 u32 pattrb11;
581 u32 pattrbeli11;
582 u32 pmd12;
583 u8 res61[4];
584 u32 pmask12;
585 u8 res62[4];
586 u32 pcntrl12;
587 u8 res63[4];
588 u32 pattrb12;
589 u32 pattrbeli12;
590 u32 pmd13;
591 u8 res64[4];
592 u32 pmask13;
593 u8 res65[4];
594 u32 pcntrl13;
595 u8 res66[4];
596 u32 pattrb13;
597 u32 pattrbeli13;
598 u32 pmd14;
599 u8 res67[4];
600 u32 pmask14;
601 u8 res68[4];
602 u32 pcntrl14;
603 u8 res69[4];
604 u32 pattrb14;
605 u32 pattrbeli14;
606 u32 pmd15;
607 u8 res70[4];
608 u32 pmask15;
609 u8 res71[4];
610 u32 pcntrl15;
611 u8 res72[4];
612 u32 pattrb15;
613 u32 pattrbeli15;
614 u8 res73[248];
615 u32 attr;
616 u32 attreli;
617 u8 res74[1024];
618} ccsr_tsec_t;
619
620
621typedef struct ccsr_pic {
622 u8 res1[64];
623 u32 ipidr0;
624 u8 res2[12];
625 u32 ipidr1;
626 u8 res3[12];
627 u32 ipidr2;
628 u8 res4[12];
629 u32 ipidr3;
630 u8 res5[12];
631 u32 ctpr;
632 u8 res6[12];
633 u32 whoami;
634 u8 res7[12];
635 u32 iack;
636 u8 res8[12];
637 u32 eoi;
638 u8 res9[3916];
639 u32 frr;
640 u8 res10[28];
641 u32 gcr;
642#define MPC85xx_PICGCR_RST 0x80000000
643#define MPC85xx_PICGCR_M 0x20000000
644 u8 res11[92];
645 u32 vir;
646 u8 res12[12];
647 u32 pir;
648 u8 res13[12];
649 u32 ipivpr0;
650 u8 res14[12];
651 u32 ipivpr1;
652 u8 res15[12];
653 u32 ipivpr2;
654 u8 res16[12];
655 u32 ipivpr3;
656 u8 res17[12];
657 u32 svr;
658 u8 res18[12];
659 u32 tfrr;
660 u8 res19[12];
661 u32 gtccr0;
662 u8 res20[12];
663 u32 gtbcr0;
664 u8 res21[12];
665 u32 gtvpr0;
666 u8 res22[12];
667 u32 gtdr0;
668 u8 res23[12];
669 u32 gtccr1;
670 u8 res24[12];
671 u32 gtbcr1;
672 u8 res25[12];
673 u32 gtvpr1;
674 u8 res26[12];
675 u32 gtdr1;
676 u8 res27[12];
677 u32 gtccr2;
678 u8 res28[12];
679 u32 gtbcr2;
680 u8 res29[12];
681 u32 gtvpr2;
682 u8 res30[12];
683 u32 gtdr2;
684 u8 res31[12];
685 u32 gtccr3;
686 u8 res32[12];
687 u32 gtbcr3;
688 u8 res33[12];
689 u32 gtvpr3;
690 u8 res34[12];
691 u32 gtdr3;
692 u8 res35[268];
693 u32 tcr;
694 u8 res36[12];
695 u32 irqsr0;
696 u8 res37[12];
697 u32 irqsr1;
698 u8 res38[12];
699 u32 cisr0;
700 u8 res39[12];
701 u32 cisr1;
702 u8 res40[188];
703 u32 msgr0;
704 u8 res41[12];
705 u32 msgr1;
706 u8 res42[12];
707 u32 msgr2;
708 u8 res43[12];
709 u32 msgr3;
710 u8 res44[204];
711 u32 mer;
712 u8 res45[12];
713 u32 msr;
714 u8 res46[60140];
715 u32 eivpr0;
716 u8 res47[12];
717 u32 eidr0;
718 u8 res48[12];
719 u32 eivpr1;
720 u8 res49[12];
721 u32 eidr1;
722 u8 res50[12];
723 u32 eivpr2;
724 u8 res51[12];
725 u32 eidr2;
726 u8 res52[12];
727 u32 eivpr3;
728 u8 res53[12];
729 u32 eidr3;
730 u8 res54[12];
731 u32 eivpr4;
732 u8 res55[12];
733 u32 eidr4;
734 u8 res56[12];
735 u32 eivpr5;
736 u8 res57[12];
737 u32 eidr5;
738 u8 res58[12];
739 u32 eivpr6;
740 u8 res59[12];
741 u32 eidr6;
742 u8 res60[12];
743 u32 eivpr7;
744 u8 res61[12];
745 u32 eidr7;
746 u8 res62[12];
747 u32 eivpr8;
748 u8 res63[12];
749 u32 eidr8;
750 u8 res64[12];
751 u32 eivpr9;
752 u8 res65[12];
753 u32 eidr9;
754 u8 res66[12];
755 u32 eivpr10;
756 u8 res67[12];
757 u32 eidr10;
758 u8 res68[12];
759 u32 eivpr11;
760 u8 res69[12];
761 u32 eidr11;
762 u8 res70[140];
763 u32 iivpr0;
764 u8 res71[12];
765 u32 iidr0;
766 u8 res72[12];
767 u32 iivpr1;
768 u8 res73[12];
769 u32 iidr1;
770 u8 res74[12];
771 u32 iivpr2;
772 u8 res75[12];
773 u32 iidr2;
774 u8 res76[12];
775 u32 iivpr3;
776 u8 res77[12];
777 u32 iidr3;
778 u8 res78[12];
779 u32 iivpr4;
780 u8 res79[12];
781 u32 iidr4;
782 u8 res80[12];
783 u32 iivpr5;
784 u8 res81[12];
785 u32 iidr5;
786 u8 res82[12];
787 u32 iivpr6;
788 u8 res83[12];
789 u32 iidr6;
790 u8 res84[12];
791 u32 iivpr7;
792 u8 res85[12];
793 u32 iidr7;
794 u8 res86[12];
795 u32 iivpr8;
796 u8 res87[12];
797 u32 iidr8;
798 u8 res88[12];
799 u32 iivpr9;
800 u8 res89[12];
801 u32 iidr9;
802 u8 res90[12];
803 u32 iivpr10;
804 u8 res91[12];
805 u32 iidr10;
806 u8 res92[12];
807 u32 iivpr11;
808 u8 res93[12];
809 u32 iidr11;
810 u8 res94[12];
811 u32 iivpr12;
812 u8 res95[12];
813 u32 iidr12;
814 u8 res96[12];
815 u32 iivpr13;
816 u8 res97[12];
817 u32 iidr13;
818 u8 res98[12];
819 u32 iivpr14;
820 u8 res99[12];
821 u32 iidr14;
822 u8 res100[12];
823 u32 iivpr15;
824 u8 res101[12];
825 u32 iidr15;
826 u8 res102[12];
827 u32 iivpr16;
828 u8 res103[12];
829 u32 iidr16;
830 u8 res104[12];
831 u32 iivpr17;
832 u8 res105[12];
833 u32 iidr17;
834 u8 res106[12];
835 u32 iivpr18;
836 u8 res107[12];
837 u32 iidr18;
838 u8 res108[12];
839 u32 iivpr19;
840 u8 res109[12];
841 u32 iidr19;
842 u8 res110[12];
843 u32 iivpr20;
844 u8 res111[12];
845 u32 iidr20;
846 u8 res112[12];
847 u32 iivpr21;
848 u8 res113[12];
849 u32 iidr21;
850 u8 res114[12];
851 u32 iivpr22;
852 u8 res115[12];
853 u32 iidr22;
854 u8 res116[12];
855 u32 iivpr23;
856 u8 res117[12];
857 u32 iidr23;
858 u8 res118[12];
859 u32 iivpr24;
860 u8 res119[12];
861 u32 iidr24;
862 u8 res120[12];
863 u32 iivpr25;
864 u8 res121[12];
865 u32 iidr25;
866 u8 res122[12];
867 u32 iivpr26;
868 u8 res123[12];
869 u32 iidr26;
870 u8 res124[12];
871 u32 iivpr27;
872 u8 res125[12];
873 u32 iidr27;
874 u8 res126[12];
875 u32 iivpr28;
876 u8 res127[12];
877 u32 iidr28;
878 u8 res128[12];
879 u32 iivpr29;
880 u8 res129[12];
881 u32 iidr29;
882 u8 res130[12];
883 u32 iivpr30;
884 u8 res131[12];
885 u32 iidr30;
886 u8 res132[12];
887 u32 iivpr31;
888 u8 res133[12];
889 u32 iidr31;
890 u8 res134[4108];
891 u32 mivpr0;
892 u8 res135[12];
893 u32 midr0;
894 u8 res136[12];
895 u32 mivpr1;
896 u8 res137[12];
897 u32 midr1;
898 u8 res138[12];
899 u32 mivpr2;
900 u8 res139[12];
901 u32 midr2;
902 u8 res140[12];
903 u32 mivpr3;
904 u8 res141[12];
905 u32 midr3;
906 u8 res142[59852];
907 u32 ipi0dr0;
908 u8 res143[12];
909 u32 ipi0dr1;
910 u8 res144[12];
911 u32 ipi0dr2;
912 u8 res145[12];
913 u32 ipi0dr3;
914 u8 res146[12];
915 u32 ctpr0;
916 u8 res147[12];
917 u32 whoami0;
918 u8 res148[12];
919 u32 iack0;
920 u8 res149[12];
921 u32 eoi0;
922 u8 res150[130892];
923} ccsr_pic_t;
924
925
926#ifndef CONFIG_CPM2
927typedef struct ccsr_cpm {
928 u8 res[262144];
929} ccsr_cpm_t;
930#else
931
932
933
934
935typedef struct ccsr_cpm_siu {
936 u8 res1[80];
937 u32 smaer;
938 u32 smser;
939 u32 smevr;
940 u8 res2[4];
941 u32 lmaer;
942 u32 lmser;
943 u32 lmevr;
944 u8 res3[2964];
945} ccsr_cpm_siu_t;
946
947
948typedef struct ccsr_cpm_intctl {
949 u16 sicr;
950 u8 res1[2];
951 u32 sivec;
952 u32 sipnrh;
953 u32 sipnrl;
954 u32 siprr;
955 u32 scprrh;
956 u32 scprrl;
957 u32 simrh;
958 u32 simrl;
959 u32 siexr;
960 u8 res2[88];
961 u32 sccr;
962 u8 res3[124];
963} ccsr_cpm_intctl_t;
964
965
966typedef struct ccsr_cpm_iop {
967 u32 pdira;
968 u32 ppara;
969 u32 psora;
970 u32 podra;
971 u32 pdata;
972 u8 res1[12];
973 u32 pdirb;
974 u32 pparb;
975 u32 psorb;
976 u32 podrb;
977 u32 pdatb;
978 u8 res2[12];
979 u32 pdirc;
980 u32 pparc;
981 u32 psorc;
982 u32 podrc;
983 u32 pdatc;
984 u8 res3[12];
985 u32 pdird;
986 u32 ppard;
987 u32 psord;
988 u32 podrd;
989 u32 pdatd;
990 u8 res4[12];
991} ccsr_cpm_iop_t;
992
993
994typedef struct ccsr_cpm_timer {
995 u8 tgcr1;
996 u8 res1[3];
997 u8 tgcr2;
998 u8 res2[11];
999 u16 tmr1;
1000 u16 tmr2;
1001 u16 trr1;
1002 u16 trr2;
1003 u16 tcr1;
1004 u16 tcr2;
1005 u16 tcn1;
1006 u16 tcn2;
1007 u16 tmr3;
1008 u16 tmr4;
1009 u16 trr3;
1010 u16 trr4;
1011 u16 tcr3;
1012 u16 tcr4;
1013 u16 tcn3;
1014 u16 tcn4;
1015 u16 ter1;
1016 u16 ter2;
1017 u16 ter3;
1018 u16 ter4;
1019 u8 res3[608];
1020} ccsr_cpm_timer_t;
1021
1022
1023typedef struct ccsr_cpm_sdma {
1024 u8 sdsr;
1025 u8 res1[3];
1026 u8 sdmr;
1027 u8 res2[739];
1028} ccsr_cpm_sdma_t;
1029
1030
1031typedef struct ccsr_cpm_fcc1 {
1032 u32 gfmr;
1033 u32 fpsmr;
1034 u16 ftodr;
1035 u8 res1[2];
1036 u16 fdsr;
1037 u8 res2[2];
1038 u16 fcce;
1039 u8 res3[2];
1040 u16 fccm;
1041 u8 res4[2];
1042 u8 fccs;
1043 u8 res5[3];
1044 u8 ftirr_phy[4];
1045} ccsr_cpm_fcc1_t;
1046
1047
1048typedef struct ccsr_cpm_fcc2 {
1049 u32 gfmr;
1050 u32 fpsmr;
1051 u16 ftodr;
1052 u8 res1[2];
1053 u16 fdsr;
1054 u8 res2[2];
1055 u16 fcce;
1056 u8 res3[2];
1057 u16 fccm;
1058 u8 res4[2];
1059 u8 fccs;
1060 u8 res5[3];
1061 u8 ftirr_phy[4];
1062} ccsr_cpm_fcc2_t;
1063
1064
1065typedef struct ccsr_cpm_fcc3 {
1066 u32 gfmr;
1067 u32 fpsmr;
1068 u16 ftodr;
1069 u8 res1[2];
1070 u16 fdsr;
1071 u8 res2[2];
1072 u16 fcce;
1073 u8 res3[2];
1074 u16 fccm;
1075 u8 res4[2];
1076 u8 fccs;
1077 u8 res5[3];
1078 u8 res[36];
1079} ccsr_cpm_fcc3_t;
1080
1081
1082typedef struct ccsr_cpm_fcc1_ext {
1083 u32 firper;
1084 u32 firer;
1085 u32 firsr_h;
1086 u32 firsr_l;
1087 u8 gfemr;
1088 u8 res[15];
1089
1090} ccsr_cpm_fcc1_ext_t;
1091
1092
1093typedef struct ccsr_cpm_fcc2_ext {
1094 u32 firper;
1095 u32 firer;
1096 u32 firsr_h;
1097 u32 firsr_l;
1098 u8 gfemr;
1099 u8 res[31];
1100} ccsr_cpm_fcc2_ext_t;
1101
1102
1103typedef struct ccsr_cpm_fcc3_ext {
1104 u8 gfemr;
1105 u8 res[47];
1106} ccsr_cpm_fcc3_ext_t;
1107
1108
1109typedef struct ccsr_cpm_tmp1 {
1110 u8 res[496];
1111} ccsr_cpm_tmp1_t;
1112
1113
1114typedef struct ccsr_cpm_brg2 {
1115 u32 brgc5;
1116 u32 brgc6;
1117 u32 brgc7;
1118 u32 brgc8;
1119 u8 res[608];
1120} ccsr_cpm_brg2_t;
1121
1122
1123typedef struct ccsr_cpm_i2c {
1124 u8 i2mod;
1125 u8 res1[3];
1126 u8 i2add;
1127 u8 res2[3];
1128 u8 i2brg;
1129 u8 res3[3];
1130 u8 i2com;
1131 u8 res4[3];
1132 u8 i2cer;
1133 u8 res5[3];
1134 u8 i2cmr;
1135 u8 res6[331];
1136} ccsr_cpm_i2c_t;
1137
1138
1139typedef struct ccsr_cpm_cp {
1140 u32 cpcr;
1141 u32 rccr;
1142 u8 res1[14];
1143 u16 rter;
1144 u8 res2[2];
1145 u16 rtmr;
1146 u16 rtscr;
1147 u8 res3[2];
1148 u32 rtsr;
1149 u8 res4[12];
1150} ccsr_cpm_cp_t;
1151
1152
1153typedef struct ccsr_cpm_brg1 {
1154 u32 brgc1;
1155 u32 brgc2;
1156 u32 brgc3;
1157 u32 brgc4;
1158} ccsr_cpm_brg1_t;
1159
1160
1161typedef struct ccsr_cpm_scc {
1162 u32 gsmrl;
1163 u32 gsmrh;
1164 u16 psmr;
1165 u8 res1[2];
1166 u16 todr;
1167 u16 dsr;
1168 u16 scce;
1169 u8 res2[2];
1170 u16 sccm;
1171 u8 res3;
1172 u8 sccs;
1173 u8 res4[8];
1174} ccsr_cpm_scc_t;
1175
1176typedef struct ccsr_cpm_tmp2 {
1177 u8 res[32];
1178} ccsr_cpm_tmp2_t;
1179
1180
1181typedef struct ccsr_cpm_spi {
1182 u16 spmode;
1183 u8 res1[4];
1184 u8 spie;
1185 u8 res2[3];
1186 u8 spim;
1187 u8 res3[2];
1188 u8 spcom;
1189 u8 res4[82];
1190} ccsr_cpm_spi_t;
1191
1192
1193typedef struct ccsr_cpm_mux {
1194 u8 cmxsi1cr;
1195 u8 res1;
1196 u8 cmxsi2cr;
1197 u8 res2;
1198 u32 cmxfcr;
1199 u32 cmxscr;
1200 u8 res3[2];
1201 u16 cmxuar;
1202 u8 res4[16];
1203} ccsr_cpm_mux_t;
1204
1205
1206typedef struct ccsr_cpm_tmp3 {
1207 u8 res[58592];
1208} ccsr_cpm_tmp3_t;
1209
1210typedef struct ccsr_cpm_iram {
1211 u32 iram[8192];
1212 u8 res[98304];
1213} ccsr_cpm_iram_t;
1214
1215typedef struct ccsr_cpm {
1216
1217
1218
1219#define im_dprambase im_dpram1
1220 u8 im_dpram1[16*1024];
1221 u8 res1[16*1024];
1222 u8 im_dpram2[16*1024];
1223 u8 res2[16*1024];
1224 ccsr_cpm_siu_t im_cpm_siu;
1225 ccsr_cpm_intctl_t im_cpm_intctl;
1226 ccsr_cpm_iop_t im_cpm_iop;
1227 ccsr_cpm_timer_t im_cpm_timer;
1228 ccsr_cpm_sdma_t im_cpm_sdma;
1229 ccsr_cpm_fcc1_t im_cpm_fcc1;
1230 ccsr_cpm_fcc2_t im_cpm_fcc2;
1231 ccsr_cpm_fcc3_t im_cpm_fcc3;
1232 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1233 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1234 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1235 ccsr_cpm_tmp1_t im_cpm_tmp1;
1236 ccsr_cpm_brg2_t im_cpm_brg2;
1237 ccsr_cpm_i2c_t im_cpm_i2c;
1238 ccsr_cpm_cp_t im_cpm_cp;
1239 ccsr_cpm_brg1_t im_cpm_brg1;
1240 ccsr_cpm_scc_t im_cpm_scc[4];
1241 ccsr_cpm_tmp2_t im_cpm_tmp2;
1242 ccsr_cpm_spi_t im_cpm_spi;
1243 ccsr_cpm_mux_t im_cpm_mux;
1244 ccsr_cpm_tmp3_t im_cpm_tmp3;
1245 ccsr_cpm_iram_t im_cpm_iram;
1246} ccsr_cpm_t;
1247#endif
1248
1249#ifdef CONFIG_SYS_SRIO
1250
1251struct rio_arch {
1252 u32 didcar;
1253 u32 dicar;
1254 u32 aidcar;
1255 u32 aicar;
1256 u32 pefcar;
1257 u8 res0[4];
1258 u32 socar;
1259 u32 docar;
1260 u8 res1[32];
1261 u32 mcsr;
1262 u32 pwdcsr;
1263 u8 res2[4];
1264 u32 pellccsr;
1265 u8 res3[12];
1266 u32 lcsbacsr;
1267 u32 bdidcsr;
1268 u8 res4[4];
1269 u32 hbdidlcsr;
1270 u32 ctcsr;
1271};
1272
1273
1274struct rio_lp_serial_port {
1275 u32 plmreqcsr;
1276 u32 plmrespcsr;
1277 u32 plascsr;
1278 u8 res0[12];
1279 u32 pescsr;
1280 u32 pccsr;
1281};
1282
1283
1284struct rio_lp_serial {
1285 u32 pmbh0csr;
1286 u8 res0[28];
1287 u32 pltoccsr;
1288 u32 prtoccsr;
1289 u8 res1[20];
1290 u32 pgccsr;
1291 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1292};
1293
1294
1295struct rio_logical_err {
1296 u32 erbh;
1297 u8 res0[4];
1298 u32 ltledcsr;
1299 u32 ltleecsr;
1300 u8 res1[4];
1301 u32 ltlaccsr;
1302 u32 ltldidccsr;
1303 u32 ltlcccsr;
1304};
1305
1306
1307struct rio_phys_err_port {
1308 u32 edcsr;
1309 u32 erecsr;
1310 u32 ecacsr;
1311 u32 pcseccsr0;
1312 u32 peccsr[3];
1313 u8 res0[12];
1314 u32 ercsr;
1315 u32 ertcsr;
1316 u8 res1[16];
1317};
1318
1319
1320struct rio_phys_err {
1321 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1322};
1323
1324
1325struct rio_impl_common {
1326 u8 res0[4];
1327 u32 llcr;
1328 u8 res1[8];
1329 u32 epwisr;
1330 u8 res2[12];
1331 u32 lretcr;
1332 u8 res3[92];
1333 u32 pretcr;
1334 u8 res4[124];
1335};
1336
1337
1338struct rio_impl_port_spec {
1339 u32 adidcsr;
1340 u8 res0[28];
1341 u32 ptaacr;
1342 u32 lopttlcr;
1343 u8 res1[8];
1344 u32 iecsr;
1345 u8 res2[12];
1346 u32 pcr;
1347 u8 res3[20];
1348 u32 slcsr;
1349 u8 res4[4];
1350 u32 sleicr;
1351 u32 a0txcr;
1352 u32 a1txcr;
1353 u32 a2txcr;
1354 u32 mreqtxbacr[3];
1355 u32 mrspfctxbacr;
1356};
1357
1358
1359struct rio_implement {
1360 struct rio_impl_common com;
1361 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1362};
1363
1364
1365struct rio_rev_ctrl {
1366 u32 ipbrr[2];
1367};
1368
1369struct rio_atmu_row {
1370 u32 rowtar;
1371 u32 rowtear;
1372 u32 rowbar;
1373 u8 res0[4];
1374 u32 rowar;
1375 u32 rowsr[3];
1376};
1377
1378struct rio_atmu_riw {
1379 u32 riwtar;
1380 u8 res0[4];
1381 u32 riwbar;
1382 u8 res1[4];
1383 u32 riwar;
1384 u8 res2[12];
1385};
1386
1387
1388struct rio_atmu_win {
1389 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1390 u8 res0[64];
1391 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1392};
1393
1394struct rio_atmu {
1395 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1396};
1397
1398#ifdef CONFIG_SYS_FSL_RMU
1399struct rio_msg {
1400 u32 omr;
1401 u32 osr;
1402 u32 eodqdpar;
1403 u32 odqdpar;
1404 u32 eosar;
1405 u32 osar;
1406 u32 odpr;
1407 u32 odatr;
1408 u32 odcr;
1409 u32 eodqepar;
1410 u32 odqepar;
1411 u32 oretr;
1412 u32 omgr;
1413 u32 omlr;
1414 u8 res0[40];
1415 u32 imr;
1416 u32 isr;
1417 u32 eidqdpar;
1418 u32 idqdpar;
1419 u32 eifqepar;
1420 u32 ifqepar;
1421 u32 imirir;
1422 u8 res1[4];
1423 u32 eihqepar;
1424 u32 ihqepar;
1425 u8 res2[120];
1426};
1427
1428struct rio_dbell {
1429 u32 odmr;
1430 u32 odsr;
1431 u8 res0[16];
1432 u32 oddpr;
1433 u32 oddatr;
1434 u8 res1[12];
1435 u32 oddretr;
1436 u8 res2[48];
1437 u32 idmr;
1438 u32 idsr;
1439 u32 iedqdpar;
1440 u32 iqdpar;
1441 u32 iedqepar;
1442 u32 idqepar;
1443 u32 idmirir;
1444};
1445
1446struct rio_pw {
1447 u32 pwmr;
1448 u32 pwsr;
1449 u32 epwqbar;
1450 u32 pwqbar;
1451};
1452#endif
1453
1454#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1455struct rio_liodn {
1456 u32 plbr;
1457 u8 res0[28];
1458 u32 plaor;
1459 u8 res1[12];
1460 u32 pludr;
1461 u32 plldr;
1462 u8 res2[456];
1463};
1464#endif
1465
1466
1467struct ccsr_rio {
1468 struct rio_arch arch;
1469 u8 res0[144];
1470 struct rio_lp_serial lp_serial;
1471 u8 res1[1152];
1472 struct rio_logical_err logical_err;
1473 u8 res2[32];
1474 struct rio_phys_err phys_err;
1475 u8 res3[63808];
1476 struct rio_implement impl;
1477 u8 res4[2552];
1478 struct rio_rev_ctrl rev;
1479 struct rio_atmu atmu;
1480#ifdef CONFIG_SYS_FSL_RMU
1481 u8 res5[8192];
1482 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1483 u8 res6[512];
1484 struct rio_dbell dbell;
1485 u8 res7[100];
1486 struct rio_pw pw;
1487#endif
1488#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1489 u8 res5[8192];
1490 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1491#endif
1492};
1493#endif
1494
1495
1496typedef struct par_io {
1497 u32 cpodr;
1498 u32 cpdat;
1499 u32 cpdir1;
1500 u32 cpdir2;
1501 u32 cppar1;
1502 u32 cppar2;
1503 u8 res[8];
1504} par_io_t;
1505
1506#ifdef CONFIG_SYS_FSL_CPC
1507
1508
1509
1510
1511
1512
1513typedef struct cpc_corenet {
1514 u32 cpccsr0;
1515 u32 res1;
1516 u32 cpccfg0;
1517 u32 res2;
1518 u32 cpcewcr0;
1519 u32 cpcewabr0;
1520 u32 res3[2];
1521 u32 cpcewcr1;
1522 u32 cpcewabr1;
1523 u32 res4[54];
1524 u32 cpcsrcr1;
1525 u32 cpcsrcr0;
1526 u32 res5[62];
1527 struct {
1528 u32 id;
1529 u32 res;
1530 u32 alloc;
1531 u32 way;
1532 } partition_regs[16];
1533 u32 res6[704];
1534 u32 cpcerrinjhi;
1535 u32 cpcerrinjlo;
1536 u32 cpcerrinjctl;
1537 u32 res7[5];
1538 u32 cpccaptdatahi;
1539 u32 cpccaptdatalo;
1540 u32 cpcaptecc;
1541 u32 res8[5];
1542 u32 cpcerrdet;
1543 u32 cpcerrdis;
1544 u32 cpcerrinten;
1545 u32 cpcerrattr;
1546 u32 cpcerreaddr;
1547 u32 cpcerraddr;
1548 u32 cpcerrctl;
1549 u32 res9[41];
1550 u32 cpchdbcr0;
1551 u32 res10[63];
1552} cpc_corenet_t;
1553
1554#define CPC_CSR0_CE 0x80000000
1555#define CPC_CSR0_PE 0x40000000
1556#define CPC_CSR0_FI 0x00200000
1557#define CPC_CSR0_WT 0x00080000
1558#define CPC_CSR0_FL 0x00000800
1559#define CPC_CSR0_LFC 0x00000400
1560#define CPC_CFG0_SZ_MASK 0x00003fff
1561#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1562#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1563#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1564#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1565#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1566 & CPC_SRCR1_SRBARU_MASK)
1567#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1568#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1569#define CPC_SRCR0_INTLVEN 0x00000100
1570#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1571#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1572#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1573#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1574#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1575#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1576#define CPC_SRCR0_SRAMEN 0x00000001
1577#define CPC_ERRDIS_TMHITDIS 0x00000080
1578#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1579#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1580#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1581#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
1582#endif
1583
1584
1585#ifdef CONFIG_FSL_CORENET
1586typedef struct ccsr_gur {
1587 u32 porsr1;
1588 u32 porsr2;
1589#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1590#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1591#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1592#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1593#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1594#endif
1595 u8 res_008[0x20-0x8];
1596 u32 gpporcr1;
1597 u32 gpporcr2;
1598 u32 dcfg_fusesr;
1599#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1600#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1601#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1602#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1603 u8 res_02c[0x70-0x2c];
1604 u32 devdisr;
1605 u32 devdisr2;
1606 u32 devdisr3;
1607 u32 devdisr4;
1608#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1609 u32 devdisr5;
1610#define FSL_CORENET_DEVDISR_PBL 0x80000000
1611#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1612#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1613#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1614#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1615#define FSL_CORENET_DEVDISR_USB1 0x00080000
1616#define FSL_CORENET_DEVDISR_USB2 0x00040000
1617#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1618#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1619#define FSL_CORENET_DEVDISR_PME 0x00000800
1620#define FSL_CORENET_DEVDISR_SEC 0x00000200
1621#define FSL_CORENET_DEVDISR_RMU 0x00000080
1622#define FSL_CORENET_DEVDISR_DCE 0x00000040
1623#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1624#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1625#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1626#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1627#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1628#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1629#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1630#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1631#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
1632#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1633#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1634#else
1635#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1636#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1637#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1638#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1639#endif
1640#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1641#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1642#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1643#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1644#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1645#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1646#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1647#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1648#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1649#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1650#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1651#define FSL_CORENET_DEVDISR2_FM2 0x00000040
1652#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1653#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1654#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1655#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1656#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1657#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1658#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1659#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1660#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1661#define FSL_CORENET_DEVDISR3_LA1 0x00008000
1662#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1663#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1664#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1665#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1666#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1667#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1668#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1669#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1670#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1671#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1672#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1673#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1674#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1675#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1676#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1677#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1678#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1679#define FSL_CORENET_DEVDISR5_NAL 0x00100000
1680#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1681#define FSL_CORENET_NUM_DEVDISR 5
1682#else
1683#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1684#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1685#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1686#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1687#define FSL_CORENET_DEVDISR_RMU 0x08000000
1688#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1689#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1690#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1691#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1692#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1693#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1694#define FSL_CORENET_DEVDISR_DBG 0x00010000
1695#define FSL_CORENET_DEVDISR_NAL 0x00008000
1696#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1697#define FSL_CORENET_DEVDISR_SATA2 0x00002000
1698#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1699#define FSL_CORENET_DEVDISR_USB1 0x00000800
1700#define FSL_CORENET_DEVDISR_USB2 0x00000400
1701#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1702#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1703#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1704#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1705#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1706#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1707#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1708#define FSL_CORENET_DEVDISR2_PME 0x80000000
1709#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1710#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1711#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1712#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1713#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1714#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1715#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1716#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1717#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1718#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1719#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1720#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1721#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1722#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1723#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1724#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1725#define FSL_CORENET_NUM_DEVDISR 2
1726 u32 powmgtcsr;
1727#endif
1728 u8 res8[12];
1729 u32 coredisru;
1730 u32 coredisrl;
1731 u8 res9[8];
1732 u32 pvr;
1733 u32 svr;
1734 u8 res10[8];
1735 u32 rstcr;
1736 u32 rstrqpblsr;
1737 u8 res11[8];
1738 u32 rstrqmr1;
1739#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1740#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1741#endif
1742 u8 res12[4];
1743 u32 rstrqsr1;
1744 u8 res13[4];
1745 u8 res14[4];
1746 u32 rstrqwdtmrl;
1747 u8 res15[4];
1748 u32 rstrqwdtsrl;
1749 u8 res16[4];
1750 u32 brrl;
1751 u8 res17[24];
1752 u32 rcwsr[16];
1753#define RCW_SB_EN_REG_INDEX 7
1754#define RCW_SB_EN_MASK 0x00200000
1755
1756#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1757#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1758
1759#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
1760#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1761#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
1762#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1763#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1764#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1765#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1766#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1767#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1768#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1769#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1770#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1771#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
1772#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1773#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1774#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1775#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1776#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1777#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
1778#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1779#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1780#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1781#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1782#define FSL_CORENET_RCWSR13_EC1 0x30000000
1783#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1784#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1785#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1786#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1787#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1788#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
1789#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1790#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1791#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
1792#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1793#define PXCKEN_MASK 0x80000000
1794#define PXCK_MASK 0x00FF0000
1795#define PXCK_BITS_START 16
1796#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
1797#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1798#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
1799#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1800#define FSL_CORENET_RCWSR13_EC1 0x30000000
1801#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1802#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1803#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1804#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
1805#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1806#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
1807#define PXCKEN_MASK 0x80000000
1808#define PXCK_MASK 0x00FF0000
1809#define PXCK_BITS_START 16
1810#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
1811#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1812#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1813#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1814#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1815#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1816#endif
1817#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1818#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1819#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1820#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1821#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1822#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1823#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1824#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1825#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1826#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1827#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1828
1829#else
1830#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1831#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1832#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1833#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1834#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1835#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1836#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1837#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1838#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000
1839#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000
1840#endif
1841
1842#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1843#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1844#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1845#define FSL_CORENET_RCWSR11_EC1 0x00c00000
1846#ifdef CONFIG_ARCH_P4080
1847#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1848#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1849#define FSL_CORENET_RCWSR11_EC2 0x001c0000
1850#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1851#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1852#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1853#endif
1854#if defined(CONFIG_ARCH_P2041) || \
1855 defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
1856#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1857#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1858#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1859#define FSL_CORENET_RCWSR11_EC2 0x00180000
1860#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1861#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1862#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1863#endif
1864#if defined(CONFIG_ARCH_P5040)
1865#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1866#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1867#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1868#define FSL_CORENET_RCWSR11_EC2 0x00180000
1869#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1870#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1871#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1872#endif
1873#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
1874#define FSL_CORENET_RCWSR13_EC1 0x60000000
1875#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1876#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1877#define FSL_CORENET_RCWSR13_EC2 0x18000000
1878#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1879#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1880#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1881#endif
1882#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
1883#define FSL_CORENET_RCWSR13_EC1 0x60000000
1884#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1885#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1886#define FSL_CORENET_RCWSR13_EC2 0x18000000
1887#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1888#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1889#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1890#endif
1891 u8 res18[192];
1892 u32 scratchrw[4];
1893 u8 res19[240];
1894 u32 scratchw1r[4];
1895 u8 res20[240];
1896 u32 scrtsr[8];
1897 u8 res21[224];
1898 u32 pex1liodnr;
1899 u32 pex2liodnr;
1900 u32 pex3liodnr;
1901 u32 pex4liodnr;
1902 u32 rio1liodnr;
1903 u32 rio2liodnr;
1904 u32 rio3liodnr;
1905 u32 rio4liodnr;
1906 u32 usb1liodnr;
1907 u32 usb2liodnr;
1908 u32 usb3liodnr;
1909 u32 usb4liodnr;
1910 u32 sdmmc1liodnr;
1911 u32 sdmmc2liodnr;
1912 u32 sdmmc3liodnr;
1913 u32 sdmmc4liodnr;
1914 u32 rio1maintliodnr;
1915 u32 rio2maintliodnr;
1916 u32 rio3maintliodnr;
1917 u32 rio4maintliodnr;
1918 u32 sata1liodnr;
1919 u32 sata2liodnr;
1920 u32 sata3liodnr;
1921 u32 sata4liodnr;
1922 u8 res22[20];
1923 u32 tdmliodnr;
1924 u32 qeliodnr;
1925 u8 res_57c[4];
1926 u32 dma1liodnr;
1927 u32 dma2liodnr;
1928 u32 dma3liodnr;
1929 u32 dma4liodnr;
1930 u8 res23[48];
1931 u8 res24[64];
1932 u32 pblsr;
1933 u32 pamubypenr;
1934 u32 dmacr1;
1935 u8 res25[4];
1936 u32 gensr1;
1937 u8 res26[12];
1938 u32 gencr1;
1939 u8 res27[12];
1940 u8 res28[4];
1941 u32 cgensrl;
1942 u8 res29[8];
1943 u8 res30[4];
1944 u32 cgencrl;
1945 u8 res31[184];
1946 u32 sriopstecr;
1947 u32 dcsrcr;
1948 u8 res31a[56];
1949 u32 tp_ityp[64];
1950 struct {
1951 u32 upper;
1952 u32 lower;
1953 } tp_cluster[16];
1954 u8 res32[1344];
1955 u32 pmuxcr;
1956 u8 res33[60];
1957 u32 iovselsr;
1958 u8 res34[28];
1959 u32 ddrclkdr;
1960 u8 res35;
1961 u32 elbcclkdr;
1962 u8 res36[20];
1963 u32 sdhcpcr;
1964 u8 res37[380];
1965} ccsr_gur_t;
1966
1967#define TP_ITYP_AV 0x00000001
1968#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)
1969#define TP_ITYP_TYPE_OTHER 0x0
1970#define TP_ITYP_TYPE_PPC 0x1
1971#define TP_ITYP_TYPE_SC 0x2
1972#define TP_ITYP_TYPE_HA 0x3
1973#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)
1974#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5)
1975
1976#define TP_CLUSTER_EOC 0x80000000
1977#define TP_CLUSTER_INIT_MASK 0x0000003f
1978#define TP_INIT_PER_CLUSTER 4
1979
1980#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1981#define FSL_CORENET_DCSR_SZ_4M 0x0
1982#define FSL_CORENET_DCSR_SZ_1G 0x3
1983
1984
1985
1986
1987
1988#define rmuliodnr rio1maintliodnr
1989
1990typedef struct ccsr_clk {
1991 struct {
1992 u32 clkcncsr;
1993 u8 res_004[0x0c];
1994 u32 clkcgnhwacsr;
1995 u8 res_014[0x0c];
1996 } clkcsr[12];
1997 u8 res_100[0x680];
1998 struct {
1999 u32 pllcngsr;
2000 u8 res10[0x1c];
2001 } pllcgsr[12];
2002 u8 res21[0x280];
2003 u32 pllpgsr;
2004 u8 res16[0x1c];
2005 u32 plldgsr;
2006 u8 res17[0x3dc];
2007} ccsr_clk_t;
2008
2009#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2010typedef struct ccsr_rcpm {
2011 u8 res_00[12];
2012 u32 tph10sr0;
2013 u8 res_10[12];
2014 u32 tph10setr0;
2015 u8 res_20[12];
2016 u32 tph10clrr0;
2017 u8 res_30[12];
2018 u32 tph10psr0;
2019 u8 res_40[12];
2020 u32 twaitsr0;
2021 u8 res_50[96];
2022 u32 pcph15sr;
2023 u32 pcph15setr;
2024 u32 pcph15clrr;
2025 u32 pcph15psr;
2026 u8 res_c0[16];
2027 u32 pcph20sr;
2028 u32 pcph20setr;
2029 u32 pcph20clrr;
2030 u32 pcph20psr;
2031 u32 pcpw20sr;
2032 u8 res_e0[12];
2033 u32 pcph30sr;
2034 u32 pcph30setr;
2035 u32 pcph30clrr;
2036 u32 pcph30psr;
2037 u8 res_100[32];
2038 u32 ippwrgatecr;
2039 u8 res_124[12];
2040 u32 powmgtcsr;
2041 u8 res_134[12];
2042 u32 ippdexpcr[4];
2043 u8 res_150[12];
2044 u32 tpmimr0;
2045 u8 res_160[12];
2046 u32 tpmcimr0;
2047 u8 res_170[12];
2048 u32 tpmmcmr0;
2049 u8 res_180[12];
2050 u32 tpmnmimr0;
2051 u8 res_190[12];
2052 u32 tmcpmaskcr0;
2053 u32 pctbenr;
2054 u32 pctbclkselr;
2055 u32 tbclkdivr;
2056 u8 res_1ac[4];
2057 u32 ttbhltcr[4];
2058 u32 clpcl10sr;
2059 u32 clpcl10setr;
2060 u32 clpcl10clrr;
2061 u32 clpcl10psr;
2062 u32 cddslpsetr;
2063 u32 cddslpclrr;
2064 u32 cdpwroksetr;
2065 u32 cdpwrokclrr;
2066 u32 cdpwrensr;
2067 u32 cddslsr;
2068 u8 res_1e8[8];
2069 u32 dslpcntcr[8];
2070 u8 res_300[3568];
2071} ccsr_rcpm_t;
2072
2073#define ctbenrl pctbenr
2074
2075#else
2076typedef struct ccsr_rcpm {
2077 u8 res1[4];
2078 u32 cdozsrl;
2079 u8 res2[4];
2080 u32 cdozcrl;
2081 u8 res3[4];
2082 u32 cnapsrl;
2083 u8 res4[4];
2084 u32 cnapcrl;
2085 u8 res5[4];
2086 u32 cdozpsrl;
2087 u8 res6[4];
2088 u32 cdozpcrl;
2089 u8 res7[4];
2090 u32 cwaitsrl;
2091 u8 res8[8];
2092 u32 powmgtcsr;
2093 u8 res9[12];
2094 u32 ippdexpcr0;
2095 u8 res10[12];
2096 u8 res11[4];
2097 u32 cpmimrl;
2098 u8 res12[4];
2099 u32 cpmcimrl;
2100 u8 res13[4];
2101 u32 cpmmcimrl;
2102 u8 res14[4];
2103 u32 cpmnmimrl;
2104 u8 res15[4];
2105 u32 ctbenrl;
2106 u8 res16[4];
2107 u32 ctbclkselrl;
2108 u8 res17[4];
2109 u32 ctbhltcrl;
2110 u8 res18[0xf68];
2111} ccsr_rcpm_t;
2112#endif
2113
2114#else
2115typedef struct ccsr_gur {
2116 u32 porpllsr;
2117#ifdef CONFIG_ARCH_MPC8536
2118#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2119#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2120#elif defined(CONFIG_ARCH_C29X)
2121#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2122#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2123 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2124 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2125#else
2126#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2127#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2128#else
2129#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2130#endif
2131#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2132#endif
2133#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2134#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2135#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2136#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2137 u32 porbmsr;
2138#define MPC85xx_PORBMSR_HA 0x00070000
2139#define MPC85xx_PORBMSR_HA_SHIFT 16
2140#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2141#define PORBMSR_ROMLOC_SPI 0x6
2142#define PORBMSR_ROMLOC_SDHC 0x7
2143#define PORBMSR_ROMLOC_NAND_2K 0x9
2144#define PORBMSR_ROMLOC_NOR 0xf
2145 u32 porimpscr;
2146 u32 pordevsr;
2147#if defined(CONFIG_ARCH_P1023)
2148#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2149#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2150#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2151#else
2152#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2153#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2154#endif
2155#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2156#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2157#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2158#define MPC85xx_PORDEVSR_PCI1 0x00800000
2159#if defined(CONFIG_ARCH_P1022)
2160#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2161#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2162#elif defined(CONFIG_ARCH_P1023)
2163#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2164#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2165#else
2166#if defined(CONFIG_ARCH_P1010)
2167#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2168#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2169#elif defined(CONFIG_ARCH_BSC9132)
2170#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2171#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2172#elif defined(CONFIG_ARCH_C29X)
2173#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2174#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2175#else
2176#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2177#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2178#endif
2179#endif
2180#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2181#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2182#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2183#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2184#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2185#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2186#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2187#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2188 u32 pordbgmsr;
2189 u32 pordevsr2;
2190#if defined(CONFIG_ARCH_C29X)
2191#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2192#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2193#endif
2194#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
2195
2196#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2197 u8 res1[8];
2198 u32 gpporcr;
2199 u8 res2[12];
2200#if defined(CONFIG_ARCH_MPC8536)
2201 u32 gencfgr;
2202#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2203#else
2204 u32 gpiocr;
2205#endif
2206 u8 res3[12];
2207#if defined(CONFIG_ARCH_MPC8569)
2208 u32 plppar1;
2209 u32 plppar2;
2210 u32 plpdir1;
2211 u32 plpdir2;
2212#else
2213 u32 gpoutdr;
2214 u8 res4[12];
2215#endif
2216 u32 gpindr;
2217 u8 res5[12];
2218 u32 pmuxcr;
2219#if defined(CONFIG_ARCH_P1010)
2220#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2221#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2222#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2223#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2224#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2225#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2226#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2227#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2228#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2229#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2230#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2231#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2232#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2233#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2234#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2235#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2236#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2237#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2238#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2239#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2240#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2241#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2242#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2243#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2244#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2245#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2246#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2247#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2248#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2249#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2250#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2251#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2252#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2253#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2254#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2255#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2256#define MPC85xx_PMUXCR_SPI_RES 0x00000030
2257#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2258#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2259#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2260#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2261#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2262#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2263#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2264#endif
2265#if defined(CONFIG_ARCH_P1023)
2266#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2267#else
2268#define MPC85xx_PMUXCR_SD_DATA 0x80000000
2269#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2270#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2271#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2272#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2273#define MPC85xx_PMUXCR_QE0 0x00008000
2274#define MPC85xx_PMUXCR_QE1 0x00004000
2275#define MPC85xx_PMUXCR_QE2 0x00002000
2276#define MPC85xx_PMUXCR_QE3 0x00001000
2277#define MPC85xx_PMUXCR_QE4 0x00000800
2278#define MPC85xx_PMUXCR_QE5 0x00000400
2279#define MPC85xx_PMUXCR_QE6 0x00000200
2280#define MPC85xx_PMUXCR_QE7 0x00000100
2281#define MPC85xx_PMUXCR_QE8 0x00000080
2282#define MPC85xx_PMUXCR_QE9 0x00000040
2283#define MPC85xx_PMUXCR_QE10 0x00000020
2284#define MPC85xx_PMUXCR_QE11 0x00000010
2285#define MPC85xx_PMUXCR_QE12 0x00000008
2286#endif
2287#if defined(CONFIG_ARCH_P1022)
2288#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2289#define MPC85xx_PMUXCR_TDM 0x00014800
2290#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2291#define MPC85xx_PMUXCR_SPI 0x00000000
2292#endif
2293#if defined(CONFIG_ARCH_BSC9131)
2294#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2295#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2296#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2297#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2298#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2299#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2300#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2301#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2302#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2303#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2304#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2305#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2306#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2307#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2308#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2309#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2310#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2311#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2312#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2313#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2314#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2315#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2316#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2317#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2318#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2319#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2320#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2321#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2322#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2323#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2324#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2325#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2326#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2327#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2328#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2329#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2330#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2331#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2332#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2333#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2334#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2335#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2336#endif
2337#ifdef CONFIG_ARCH_BSC9132
2338#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2339#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2340#endif
2341#if defined(CONFIG_ARCH_C29X)
2342#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2343#define MPC85xx_PMUXCR_SPI 0x00000000
2344#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2345#endif
2346 u32 pmuxcr2;
2347#if defined(CONFIG_ARCH_P1010)
2348#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2349#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2350#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2351#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2352#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2353#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2354#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2355#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2356#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2357#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2358#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2359#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2360#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2361#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2362#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2363#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2364#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2365#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2366#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2367#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2368#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2369#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2370#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2371#endif
2372#if defined(CONFIG_ARCH_P1022)
2373#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2374#define MPC85xx_PMUXCR2_USB 0x00150000
2375#endif
2376#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2377#if defined(CONFIG_ARCH_BSC9131)
2378#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2379#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2380#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2381#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2382#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2383#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2384#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2385#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2386#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2387#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2388#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2389#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2390#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2391#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2392#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2393#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2394#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2395#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2396#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2397#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2398#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2399#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2400#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2401#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2402#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2403#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2404#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2405#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2406#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2407#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2408#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2409#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2410#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2411#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2412#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2413#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2414#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2415#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2416#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2417#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2418#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2419#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2420#endif
2421 u32 pmuxcr3;
2422#if defined(CONFIG_ARCH_BSC9131)
2423#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2424#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2425#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2426#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2427#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2428#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2429#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2430#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2431#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2432#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2433#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2434#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2435#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2436#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2437#endif
2438#ifdef CONFIG_ARCH_BSC9132
2439#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2440#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2441#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2442#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2443#endif
2444 u32 pmuxcr4;
2445#else
2446 u8 res6[8];
2447#endif
2448 u32 devdisr;
2449#define MPC85xx_DEVDISR_PCI1 0x80000000
2450#define MPC85xx_DEVDISR_PCI2 0x40000000
2451#define MPC85xx_DEVDISR_PCIE 0x20000000
2452#define MPC85xx_DEVDISR_LBC 0x08000000
2453#define MPC85xx_DEVDISR_PCIE2 0x04000000
2454#define MPC85xx_DEVDISR_PCIE3 0x02000000
2455#define MPC85xx_DEVDISR_SEC 0x01000000
2456#define MPC85xx_DEVDISR_SRIO 0x00080000
2457#define MPC85xx_DEVDISR_RMSG 0x00040000
2458#define MPC85xx_DEVDISR_DDR 0x00010000
2459#define MPC85xx_DEVDISR_CPU 0x00008000
2460#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2461#define MPC85xx_DEVDISR_TB 0x00004000
2462#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2463#define MPC85xx_DEVDISR_CPU1 0x00002000
2464#define MPC85xx_DEVDISR_TB1 0x00001000
2465#define MPC85xx_DEVDISR_DMA 0x00000400
2466#define MPC85xx_DEVDISR_TSEC1 0x00000080
2467#define MPC85xx_DEVDISR_TSEC2 0x00000040
2468#define MPC85xx_DEVDISR_TSEC3 0x00000020
2469#define MPC85xx_DEVDISR_TSEC4 0x00000010
2470#define MPC85xx_DEVDISR_I2C 0x00000004
2471#define MPC85xx_DEVDISR_DUART 0x00000002
2472 u8 res7[12];
2473 u32 powmgtcsr;
2474 u8 res8[12];
2475 u32 mcpsumr;
2476 u8 res9[12];
2477 u32 pvr;
2478 u32 svr;
2479 u8 res10[8];
2480 u32 rstcr;
2481#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
2482 u8 res11a[76];
2483 par_io_t qe_par_io[7];
2484 u8 res11b[1600];
2485#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
2486 u8 res11a[12];
2487 u32 iovselsr;
2488 u8 res11b[60];
2489 par_io_t qe_par_io[3];
2490 u8 res11c[1496];
2491#else
2492 u8 res11a[1868];
2493#endif
2494 u32 clkdvdr;
2495 u8 res12[1532];
2496 u32 clkocr;
2497 u8 res13[12];
2498 u32 ddrdllcr;
2499 u8 res14[12];
2500 u32 lbcdllcr;
2501#if defined(CONFIG_ARCH_BSC9131)
2502 u8 res15[12];
2503 u32 halt_req_mask;
2504#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2505 u8 res18[232];
2506#else
2507 u8 res15[248];
2508#endif
2509 u32 lbiuiplldcr0;
2510 u32 lbiuiplldcr1;
2511 u32 ddrioovcr;
2512 u32 tsec12ioovcr;
2513 u32 tsec34ioovcr;
2514 u8 res16[52];
2515 u32 sdhcdcr;
2516 u8 res17[61592];
2517} ccsr_gur_t;
2518#endif
2519
2520#define SDHCDCR_CD_INV 0x80000000
2521
2522#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2523#define MAX_SERDES 4
2524#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
2525#define SRDS_MAX_LANES 4
2526#else
2527#define SRDS_MAX_LANES 8
2528#endif
2529#define SRDS_MAX_BANK 2
2530typedef struct serdes_corenet {
2531 struct {
2532 u32 rstctl;
2533#define SRDS_RSTCTL_RST 0x80000000
2534#define SRDS_RSTCTL_RSTDONE 0x40000000
2535#define SRDS_RSTCTL_RSTERR 0x20000000
2536#define SRDS_RSTCTL_SWRST 0x10000000
2537#define SRDS_RSTCTL_SDEN 0x00000020
2538#define SRDS_RSTCTL_SDRST_B 0x00000040
2539#define SRDS_RSTCTL_PLLRST_B 0x00000080
2540#define SRDS_RSTCTL_RSTERR_SHIFT 29
2541 u32 pllcr0;
2542#define SRDS_PLLCR0_POFF 0x80000000
2543#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2544#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2545#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2546#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2547#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2548#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2549#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2550#define SRDS_PLLCR0_PLL_LCK 0x00800000
2551#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2552#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2553#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2554#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
2555#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2556#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2557#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2558#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2559#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2560#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
2561#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2562#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2563 u32 pllcr1;
2564#define SRDS_PLLCR1_BCAP_EN 0x20000000
2565#define SRDS_PLLCR1_BCAP_OVD 0x10000000
2566#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2567#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2568#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2569#define SRDS_PLLCR1_BYP_CAL 0x02000000
2570 u32 pllsr2;
2571#define SRDS_PLLSR2_BCAP_EN 0x00800000
2572#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2573#define SRDS_PLLSR2_FCAP 0x003F0000
2574#define SRDS_PLLSR2_FCAP_SHIFT 16
2575#define SRDS_PLLSR2_DCBIAS 0x000F0000
2576#define SRDS_PLLSR2_DCBIAS_SHIFT 16
2577 u32 pllcr3;
2578 u32 pllcr4;
2579 u8 res_18[0x20-0x18];
2580 } bank[2];
2581 u8 res_40[0x90-0x40];
2582 u32 srdstcalcr;
2583 u8 res_94[0xa0-0x94];
2584 u32 srdsrcalcr;
2585 u8 res_a4[0xb0-0xa4];
2586 u32 srdsgr0;
2587 u8 res_b4[0xe0-0xb4];
2588 u32 srdspccr0;
2589 u32 srdspccr1;
2590 u32 srdspccr2;
2591 u32 srdspccr3;
2592 u32 srdspccr4;
2593 u8 res_f4[0x100-0xf4];
2594 struct {
2595 u32 lnpssr;
2596 u8 res_104[0x120-0x104];
2597 } srdslnpssr[8];
2598 u8 res_200[0x800-0x200];
2599 struct {
2600 u32 gcr0;
2601 u32 gcr1;
2602 u32 gcr2;
2603 u32 res_80c;
2604 u32 recr0;
2605 u32 res_814;
2606 u32 tecr0;
2607 u32 res_81c;
2608 u32 ttlcr0;
2609 u8 res_824[0x840-0x824];
2610 } lane[8];
2611 u8 res_a00[0x1000-0xa00];
2612} serdes_corenet_t;
2613
2614#else
2615
2616#define SRDS_MAX_LANES 18
2617#define SRDS_MAX_BANK 3
2618typedef struct serdes_corenet {
2619 struct {
2620 u32 rstctl;
2621#define SRDS_RSTCTL_RST 0x80000000
2622#define SRDS_RSTCTL_RSTDONE 0x40000000
2623#define SRDS_RSTCTL_RSTERR 0x20000000
2624#define SRDS_RSTCTL_SDPD 0x00000020
2625 u32 pllcr0;
2626#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2627#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2628#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2629#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2630#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2631#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2632#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2633#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2634#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2635#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2636 u32 pllcr1;
2637#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2638 u32 res[5];
2639 } bank[3];
2640 u32 res1[12];
2641 u32 srdstcalcr;
2642 u32 res2[3];
2643 u32 srdsrcalcr;
2644 u32 res3[3];
2645 u32 srdsgr0;
2646 u32 res4[11];
2647 u32 srdspccr0;
2648 u32 srdspccr1;
2649 u32 srdspccr2;
2650#define SRDS_PCCR2_RST_XGMII1 0x00800000
2651#define SRDS_PCCR2_RST_XGMII2 0x00400000
2652 u32 res5[197];
2653 struct serdes_lane {
2654 u32 gcr0;
2655#define SRDS_GCR0_RRST 0x00400000
2656#define SRDS_GCR0_1STLANE 0x00010000
2657#define SRDS_GCR0_UOTHL 0x00100000
2658 u32 gcr1;
2659#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2660#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2661#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2662#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2663#define SRDS_GCR1_OPAD_CTL 0x04000000
2664 u32 res1[4];
2665 u32 tecr0;
2666#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2667#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2668 u32 res3;
2669 u32 ttlcr0;
2670#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2671#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2672#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2673#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2674#define SRDS_TTLCR0_PM_DIS 0x00004000
2675#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2676 u32 res4[7];
2677 } lane[24];
2678 u32 res6[384];
2679} serdes_corenet_t;
2680#endif
2681
2682enum {
2683 FSL_SRDS_B1_LANE_A = 0,
2684 FSL_SRDS_B1_LANE_B = 1,
2685 FSL_SRDS_B1_LANE_C = 2,
2686 FSL_SRDS_B1_LANE_D = 3,
2687 FSL_SRDS_B1_LANE_E = 4,
2688 FSL_SRDS_B1_LANE_F = 5,
2689 FSL_SRDS_B1_LANE_G = 6,
2690 FSL_SRDS_B1_LANE_H = 7,
2691 FSL_SRDS_B1_LANE_I = 8,
2692 FSL_SRDS_B1_LANE_J = 9,
2693 FSL_SRDS_B2_LANE_A = 16,
2694 FSL_SRDS_B2_LANE_B = 17,
2695 FSL_SRDS_B2_LANE_C = 18,
2696 FSL_SRDS_B2_LANE_D = 19,
2697 FSL_SRDS_B3_LANE_A = 20,
2698 FSL_SRDS_B3_LANE_B = 21,
2699 FSL_SRDS_B3_LANE_C = 22,
2700 FSL_SRDS_B3_LANE_D = 23,
2701};
2702
2703typedef struct ccsr_pme {
2704 u8 res0[0x804];
2705 u32 liodnbr;
2706 u8 res1[0x1f8];
2707 u32 srcidr;
2708 u8 res2[8];
2709 u32 liodnr;
2710 u8 res3[0x1e8];
2711 u32 pm_ip_rev_1;
2712 u32 pm_ip_rev_2;
2713 u8 res4[0x400];
2714} ccsr_pme_t;
2715
2716struct ccsr_pamu {
2717 u32 ppbah;
2718 u32 ppbal;
2719 u32 pplah;
2720 u32 pplal;
2721 u32 spbah;
2722 u32 spbal;
2723 u32 splah;
2724 u32 splal;
2725 u32 obah;
2726 u32 obal;
2727 u32 olah;
2728 u32 olal;
2729};
2730
2731#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2732struct ccsr_raide {
2733 u8 res0[0x543];
2734 u32 liodnbr;
2735 u8 res1[0xab8];
2736 struct {
2737 struct {
2738 u32 cfg0;
2739 u32 cfg1;
2740 u8 res1[0x3f8];
2741 } ring[2];
2742 u8 res[0x800];
2743 } jq[2];
2744};
2745#endif
2746
2747#ifdef CONFIG_SYS_DPAA_RMAN
2748struct ccsr_rman {
2749 u8 res0[0xf64];
2750 u32 mmliodnbr;
2751 u32 mmitar;
2752 u32 mmitdr;
2753 u8 res4[0x1f090];
2754};
2755#endif
2756
2757#ifdef CONFIG_SYS_PMAN
2758struct ccsr_pman {
2759 u8 res_00[0x40];
2760 u32 poes1;
2761 u32 poes2;
2762 u32 poeah;
2763 u32 poeal;
2764 u8 res_50[0x50];
2765 u32 pr1;
2766 u32 pr2;
2767 u8 res_a8[0x8];
2768 u32 pcap;
2769 u8 res_b4[0xc];
2770 u32 pc1;
2771 u32 pc2;
2772 u32 pc3;
2773 u32 pc4;
2774 u32 pc5;
2775 u32 pc6;
2776 u8 res_d8[0x8];
2777 u32 ppa1;
2778 u32 ppa2;
2779 u8 res_e8[0x8];
2780 u32 pics;
2781 u8 res_f4[0xf0c];
2782};
2783#endif
2784
2785#ifdef CONFIG_FSL_CORENET
2786#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2787#ifdef CONFIG_SYS_PMAN
2788#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2789#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2790#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2791#endif
2792#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2793#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2794#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2795#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2796#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2797#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2798
2799
2800#define CONFIG_SYS_OSPR_OFFSET 0x200
2801#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2802#else
2803#define CONFIG_SYS_SFP_OFFSET 0xE8000
2804#endif
2805#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2806#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2807#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2808#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2809#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2810#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2811#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
2812#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2813#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2814#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2815#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2816#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2817#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2818#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2819#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2820#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2821#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2822#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
2823#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2824#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
2825 !defined(CONFIG_ARCH_B4420)
2826#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2827#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2828#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2829#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2830#else
2831#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2832#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2833#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2834#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2835#endif
2836#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2837#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2838#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2839#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2840#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2841#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2842#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2843#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
2844#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
2845#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2846#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2847#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2848#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2849#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2850#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2851#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2852#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2853#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2854#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2855#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2856#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2857#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2858#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2859#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2860#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2861#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2862#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2863#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2864#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2865#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2866#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2867#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2868#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2869#else
2870#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2871#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2872#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2873#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2874#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2875#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2876#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2877#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2878#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2879#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2880#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2881#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
2882#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2883#else
2884#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2885#endif
2886#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2887#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2888#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2889#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2890#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2891#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2892#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2893#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2894#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2895#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
2896#ifdef CONFIG_TSECV2
2897#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2898#elif defined(CONFIG_TSECV2_1)
2899#define CONFIG_SYS_TSEC1_OFFSET 0x10000
2900#else
2901#define CONFIG_SYS_TSEC1_OFFSET 0x24000
2902#endif
2903#define CONFIG_SYS_MDIO1_OFFSET 0x24000
2904#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2905#if defined(CONFIG_ARCH_C29X)
2906#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2907#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
2908#else
2909#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2910#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
2911#endif
2912#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2913#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2914#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
2915#define CONFIG_SYS_SFP_OFFSET 0xE7000
2916#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2917#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2918#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2919#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2920#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2921#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2922#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2923#endif
2924
2925#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2926#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2927#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2928
2929#if defined(CONFIG_ARCH_BSC9132)
2930#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2931#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2932 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2933#endif
2934
2935#define CONFIG_SYS_FSL_CPC_ADDR \
2936 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2937#define CONFIG_SYS_FSL_SCFG_ADDR \
2938 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
2939#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
2940 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
2941#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
2942 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
2943#define CONFIG_SYS_FSL_QMAN_ADDR \
2944 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2945#define CONFIG_SYS_FSL_BMAN_ADDR \
2946 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2947#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2948 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2949#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
2950 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
2951#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
2952 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
2953#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2954 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2955#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2956 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2957#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2958 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2959#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2960 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2961#define CONFIG_SYS_MPC85xx_ECM_ADDR \
2962 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2963#define CONFIG_SYS_FSL_DDR_ADDR \
2964 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
2965#define CONFIG_SYS_FSL_DDR2_ADDR \
2966 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
2967#define CONFIG_SYS_FSL_DDR3_ADDR \
2968 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
2969#define CONFIG_SYS_LBC_ADDR \
2970 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2971#define CONFIG_SYS_IFC_ADDR \
2972 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
2973#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2974 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2975#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2976 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2977#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2978 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2979#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2980 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2981#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2982 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2983#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2984 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2985#define CONFIG_SYS_MPC85xx_L2_ADDR \
2986 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2987#define CONFIG_SYS_MPC85xx_DMA_ADDR \
2988 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2989#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2990 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
2991#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
2992 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
2993#define CONFIG_SYS_MPC85xx_CPM_ADDR \
2994 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
2995#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
2996 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
2997#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2998 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
2999#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3000 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3001#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3002 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3003#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
3004 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
3005#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
3007#define CONFIG_SYS_MPC85xx_USB1_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3009#define CONFIG_SYS_MPC85xx_USB2_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3011#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3013#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3015#define CONFIG_SYS_FSL_SEC_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3017#define CONFIG_SYS_FSL_JR0_ADDR \
3018 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
3019#define CONFIG_SYS_FSL_FM1_ADDR \
3020 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3021#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3023#define CONFIG_SYS_FSL_FM2_ADDR \
3024 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3025#define CONFIG_SYS_FSL_SRIO_ADDR \
3026 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3027#define CONFIG_SYS_PAMU_ADDR \
3028 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
3029
3030#define CONFIG_SYS_PCI1_ADDR \
3031 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3032#define CONFIG_SYS_PCI2_ADDR \
3033 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3034#define CONFIG_SYS_PCIE1_ADDR \
3035 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3036#define CONFIG_SYS_PCIE2_ADDR \
3037 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3038#define CONFIG_SYS_PCIE3_ADDR \
3039 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3040#define CONFIG_SYS_PCIE4_ADDR \
3041 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3042
3043#define CONFIG_SYS_SFP_ADDR \
3044 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
3045
3046#define CONFIG_SYS_SEC_MON_ADDR \
3047 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
3048
3049#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3050#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3051
3052#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3053struct ccsr_cluster_l2 {
3054 u32 l2csr0;
3055 u32 l2csr1;
3056 u32 l2cfg0;
3057 u8 res_0c[500];
3058 u32 l2pir0;
3059 u8 res_204[4];
3060 u32 l2par0;
3061 u32 l2pwr0;
3062 u32 l2pir1;
3063 u8 res_214[4];
3064 u32 l2par1;
3065 u32 l2pwr1;
3066 u32 u2pir2;
3067 u8 res_224[4];
3068 u32 l2par2;
3069 u32 l2pwr2;
3070 u32 l2pir3;
3071 u8 res_234[4];
3072 u32 l2par3;
3073 u32 l2pwr3;
3074 u32 l2pir4;
3075 u8 res244[4];
3076 u32 l2par4;
3077 u32 l2pwr4;
3078 u32 l2pir5;
3079 u8 res_254[4];
3080 u32 l2par5;
3081 u32 l2pwr5;
3082 u32 l2pir6;
3083 u8 res_264[4];
3084 u32 l2par6;
3085 u32 l2pwr6;
3086 u32 l2pir7;
3087 u8 res274[4];
3088 u32 l2par7;
3089 u32 l2pwr7;
3090 u8 res_280[0xb80];
3091 u32 l2errinjhi;
3092 u32 l2errinjlo;
3093 u32 l2errinjctl;
3094 u8 res_e0c[20];
3095 u32 l2captdatahi;
3096 u32 l2captdatalo;
3097 u32 l2captecc;
3098 u8 res_e2c[20];
3099 u32 l2errdet;
3100 u32 l2errdis;
3101 u32 l2errinten;
3102 u32 l2errattr;
3103 u32 l2erreaddr;
3104 u32 l2erraddr;
3105 u32 l2errctl;
3106};
3107#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3108 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3109#endif
3110
3111#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3112struct dcsr_dcfg_regs {
3113 u8 res_0[0x520];
3114 u32 ecccr1;
3115#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3116#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3117 u8 res_524[0x1000 - 0x524];
3118};
3119
3120#define CONFIG_SYS_MPC85xx_SCFG \
3121 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
3122#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3123
3124struct ccsr_scfg {
3125 u32 dpslpcr;
3126 u32 usb1dpslpcsr;
3127 u32 usb2dpslpcsr;
3128 u32 fmclkdpslpcr;
3129 u32 res1[4];
3130 u32 esgmiiselcr;
3131 u32 res2;
3132 u32 pixclkcr;
3133 u32 res3[245];
3134 u32 qeioclkcr;
3135 u32 emiiocr;
3136 u32 sdhciovselcr;
3137 u32 qmifrstcr;
3138 u32 res4[60];
3139 u32 sparecr[8];
3140};
3141#endif
3142