LXR uboot/arch/riscv/lib/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017 Andes Technology Corporation
   4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5 */
   6
   7#include <common.h>
   8#include <cpu_func.h>
   9
  10void invalidate_icache_all(void)
  11{
  12        asm volatile ("fence.i" ::: "memory");
  13}
  14
  15__weak void flush_dcache_all(void)
  16{
  17}
  18
  19__weak void flush_dcache_range(unsigned long start, unsigned long end)
  20{
  21}
  22
  23void invalidate_icache_range(unsigned long start, unsigned long end)
  24{
  25        /*
  26         * RISC-V does not have an instruction for invalidating parts of the
  27         * instruction cache. Invalidate all of it instead.
  28         */
  29        invalidate_icache_all();
  30}
  31
  32__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
  33{
  34}
  35
  36void cache_flush(void)
  37{
  38        invalidate_icache_all();
  39        flush_dcache_all();
  40}
  41
  42void flush_cache(unsigned long addr, unsigned long size)
  43{
  44        invalidate_icache_range(addr, addr + size);
  45        flush_dcache_range(addr, addr + size);
  46}
  47
  48__weak void icache_enable(void)
  49{
  50}
  51
  52__weak void icache_disable(void)
  53{
  54}
  55
  56__weak int icache_status(void)
  57{
  58        return 0;
  59}
  60
  61__weak void dcache_enable(void)
  62{
  63}
  64
  65__weak void dcache_disable(void)
  66{
  67}
  68
  69__weak int dcache_status(void)
  70{
  71        return 0;
  72}
  73