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10#include <common.h>
11#include <init.h>
12#include <asm/io.h>
13#include <env.h>
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/arch/iomux-mx35.h>
19#include <i2c.h>
20#include <linux/types.h>
21#include <asm/gpio.h>
22#include <asm/arch/sys_proto.h>
23#include <netdev.h>
24#include <fdt_support.h>
25#include <mtd_node.h>
26#include <jffs2/load_kernel.h>
27
28#ifndef CONFIG_BOARD_EARLY_INIT_F
29#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
30#endif
31
32#define CCM_CCMR_CONFIG 0x003F4208
33
34#define ESDCTL_DDR2_CONFIG 0x007FFC3F
35
36static inline void dram_wait(unsigned int count)
37{
38 volatile unsigned int wait = count;
39
40 while (wait--)
41 ;
42}
43
44DECLARE_GLOBAL_DATA_PTR;
45
46int dram_init(void)
47{
48 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
49 PHYS_SDRAM_1_SIZE);
50
51 return 0;
52}
53
54static void board_setup_sdram(void)
55{
56 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
57
58
59 writel(0x2000, &esdc->esdctl0);
60 writel(0x2000, &esdc->esdctl1);
61
62
63 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
64 13, 10, 2, 0x8080);
65}
66
67static void setup_iomux_uart3(void)
68{
69 static const iomux_v3_cfg_t uart3_pads[] = {
70 MX35_PAD_RTS2__UART3_RXD_MUX,
71 MX35_PAD_CTS2__UART3_TXD_MUX,
72 };
73
74 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
75}
76
77#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
78
79static void setup_iomux_i2c(void)
80{
81 static const iomux_v3_cfg_t i2c_pads[] = {
82 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
83 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
84
85 NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
86 NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
87 };
88
89 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
90}
91
92
93static void setup_iomux_spi(void)
94{
95 static const iomux_v3_cfg_t spi_pads[] = {
96 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
97 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
98 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
99 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
100 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
101 };
102
103 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
104}
105
106static void setup_iomux_fec(void)
107{
108 static const iomux_v3_cfg_t fec_pads[] = {
109 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
110 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
111 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
112 MX35_PAD_FEC_COL__FEC_COL,
113 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
114 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
115 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
116 MX35_PAD_FEC_MDC__FEC_MDC,
117 MX35_PAD_FEC_MDIO__FEC_MDIO,
118 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
119 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
120 MX35_PAD_FEC_CRS__FEC_CRS,
121 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
122 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
123 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
124 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
125 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
126 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
127
128 MX35_PAD_STXFS4__GPIO2_31,
129 };
130
131
132 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
133}
134
135int board_early_init_f(void)
136{
137 struct ccm_regs *ccm =
138 (struct ccm_regs *)IMX_CCM_BASE;
139
140
141 imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
142 gpio_direction_output(65, 1);
143
144
145 writel(CCM_CCMR_CONFIG, &ccm->ccmr);
146
147 writel(CCM_MPLL_532_HZ, &ccm->mpctl);
148 writel(CCM_PPLL_300_HZ, &ccm->ppctl);
149
150
151 writel(0x00001000, &ccm->pdr0);
152
153
154 board_setup_sdram();
155
156
157 writel(readl(&ccm->cgr0) |
158 MXC_CCM_CGR0_EMI_MASK |
159 MXC_CCM_CGR0_EDIO_MASK |
160 MXC_CCM_CGR0_EPIT1_MASK,
161 &ccm->cgr0);
162
163 writel(readl(&ccm->cgr1) |
164 MXC_CCM_CGR1_FEC_MASK |
165 MXC_CCM_CGR1_GPIO1_MASK |
166 MXC_CCM_CGR1_GPIO2_MASK |
167 MXC_CCM_CGR1_GPIO3_MASK |
168 MXC_CCM_CGR1_I2C1_MASK |
169 MXC_CCM_CGR1_I2C2_MASK |
170 MXC_CCM_CGR1_I2C3_MASK,
171 &ccm->cgr1);
172
173
174 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
175
176
177 setup_iomux_uart3();
178 setup_iomux_i2c();
179 setup_iomux_fec();
180 setup_iomux_spi();
181
182 return 0;
183}
184
185int board_init(void)
186{
187
188 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
189
190
191 gpio_direction_output(63, 0);
192
193 udelay(2000);
194
195 return 0;
196}
197
198u32 get_board_rev(void)
199{
200 int rev = 0;
201
202 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
203}
204
205
206
207
208
209int ft_board_setup(void *blob, struct bd_info *bd)
210{
211 static const struct node_info nodes[] = {
212 { "physmap-flash.0", MTD_DEV_TYPE_NOR, },
213 { "mxc_nand", MTD_DEV_TYPE_NAND, },
214 };
215
216 if (env_get("fdt_noauto")) {
217 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
218 return 0;
219 }
220
221 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
222
223 return 0;
224}
225
